Détails sur le séminaire

Auditorium (IMAG)
5 décembre 2016 - 17h00
New Architectures, New Compilation Problems
par Paul FEAUTRIER de LIP, Ecole Normale Supérieure de Lyon

Abstract: In the past, performance improvements were due mostly to a steady increase in processors clock frequency. Nowadays, due to physical problems realated to power dissipation, clock frequencies are limited to about 3Ghz, and better performance can only be found in more parallelism. Parallel architectures come in many varieties -- multicores, vector processors and GPU, FPGAs and ASICs -- and each one imposes its specific programming model.
In this talk, I will explain how better compilers may help alleviate these difficulties. However, since architectures evolve faster than compilers can follow, many problems still await satisfactory solutions and offer interesting research opportunities.

Les tranparents de la presentation.

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