Verimag

Détails sur le séminaire

CTL
2 octobre 2012 - 14h00
TIREX: a textual target-level intermediate representation for virtual execution environment, compiler information exchange and program analysis
par Artur Pietrek de VERIMAG



Abstract: Some environments require several compilers, for instance one for the operating system, supporting the full C/C++ norm, and one for the applications, potentially supporting less but able to derive more performance. Maintaining different compilers for a target requires considerable effort, thus it is easier to implement and maintain target-dependent optimizations in a single, external tool. This requires a way of connecting these compilers with the target-dependent optimizer, preferably passing along some internal compiler data structures that would be time-consuming, difficult or even impossible to reconstruct from assembly language for instance.
In this thesis we introduce Tirex, a Textual Intermediate Representation for EX-changing target-level information between compilers, optimizers an different tools in the compilation toolchain. Our intermediate representation contains an instruction stream of the target processor, but still keeps the explicit program structure and supports the SSA form(Static Single Assignment ). It is easily extensible and highly flexible, which allows any data to be passed for the purpose of the optimizer. We build Tirex by extending the existing Minimalist Intermediate Representation (MinIR), itself expressed as a YAML textual encoding of compiler structures. Our extensions in Tirex include: lowering the representation to a target level, conserving the program data stream, adding loop scoped information and data dependencies. Tirex is currently produced by the Open64 and the LLVM compilers, with a GCC producer under work. It is consumed by the Linear Assembly Optimizer (LAO), a specialized, target-specific, code optimizer. We show that Tirex is versatile and can be used in a variety of different applications, such as a virtual execution environment (VEE), and provides strong basis for a program analysis framework. As part of the VEE, we present an interpreter for a Static Single Assignment (SSA) form and a just-in-time (JIT) compiler. We show how interpreting a target-level representation eliminates most of the complexities of mixed-mode execution. We also explore the issues related to efficiently interpreting a SSA form program representation.



Jury:

- Mr. Jean-Claude Fernandez
Professeur, Université Joseph Fourier, Directeur de thèse

- Mr. Benoît Dupont de Dinechin
Directeur du Développement Logiciel, Kalray, Co-Directeur de thèse

- Mr. Philippe Clauss
Professeur, Université de Strasbourg, Rapporteur

- Mr. Albert Cohen
Directeur de Recherche, INRIA, Rapporteur

- Mr. Jean-Francois Méhaut
Professeur, Université Joseph Fourier, Président

- Mr. Fabrice Rastello
Chargé de recherche, INRIA, Examinateur

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