Verimag

ASSERT

FP6 IP, 2004-2008

The ASSERT project main goal is to improve the system-and-software development process for critical embedded real-time systems, in the Aerospace and Transportation domains.

 Project Objectives

The main goal is to improve the system-and-software development process for critical embedded real-time systems, in the Aerospace and Transportation domains by:

  • Identifying and developing proven critical system families architecture, using a proof based development process supported by formal notations, component models, and innovative processes and tools.
  • Developing associated building blocks that can be composed, tailored and verified in open frameworks that shall be reused and shared by European teams across multi domain projects.

 Verimag Objectives

Formal verification and simulation of AADL models (via a translation into Lustre/Scade).

 Verimag/Synchrone People Involved

— Nicolas Halbwachs (Cluster manager)
— Pascal Raymond
— Xavier Nicollin
— Erwan Jahier
— Louis Mandel

 Verimag/DCS People Involved

— Susanne Graf
— Iulian Ober

 Publications

  • [HM06] "Simulation and verification of asynchronous systems by means of a synchronous model." Nicolas Halbwachs, Louis Mandel
  • [JHR+07] "Virtual execution of AADL models via a translation into synchronous programs." Erwan Jahier, Nicolas Halbwachs, Pascal Raymond, Xavier Nicollin, David Lesens
  • [JHR09] "Synchronous Modeling and Validation of Priority Inheritance Schedulers." Erwan Jahier, Nicolas Halbwachs, Pascal Raymond

 Partners

 Other ASSERT members

— ALCATEL-Space
— ALENIA SPAZIO SpA
— Axlog Ingenierie
— BSSE
— DASSAULT Aviation
— DIT/UPM university of Madrid
— Dutch Space BV
— EADS Corporate Research Center
— EADS-Space Transportation
— MBDA France
— European Software Institute
— ETH -Swiss Federal Institute of Technology
— INTECS HRT
— CNRS-LAAS
— Prover Technology
— SciScys
— SoftwCare
— SynSpace
— Terma A/S
— TNI-Valiosys
— Vienna University of Technology.

  Financed by

Commission Européenne


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