[SLAP'06]                                                          [logo ETAPS]


Synchronous Languages, Applications, and Programming
march 25, 2006
an ETAPS'06  Satellite event  (March 25 - April 2, 2006, Vienna, Austria)





Overview
SLAP is a workshop dedicated to synchronous languages. Such languages have emerged in the 80s as a new method to design real-time embedded critical systems. There exists now a strong interest for them in industry: Lustre, Esterel, and Signal are used with success to program real-time and safety critical applications, from nuclear power plant management layer to Airbus air flight control systems. The purpose of the SLAP workshop is to bring together researchers and practitioners who work in the field of reactive systems. The workshop topics are covering all these issues: synchronous model of computation, synchronous languages and programming formalisms, compiling techniques, formal verification, test and validation of programs, case-studies, education, etc.


Topics of interest
After SLAP’2002 in Grenoble, SLAP’2003 in Porto, SLAP’2004 in Barcelona, and SLAP’2005 in Edinburgh, SLAP'06 will be the fifth workshop devoted entirely to synchronous languages, applications, and programming. It will be a satellite event of ETAPS'2006. Its purpose is to bring together researchers and practitioners who work in the field of reactive systems.
The workshop topics cover the following issues:
   - synchronous model of computation,
   - synchronous languages and programming formalisms,
   - compiling techniques,
   - formal verification,
   - test, simulation and validation of programs,
   - case-studies,
   - industrial application that fully or partially take advantage of the synchronous languages benefits,
   - using synchronous models or languages in education activities.

Format of the workshop
  • Invited talk : Dr. Marc Duranton, Principal Scientist
    Embedded Systems Architectures on Silicon (ESAS)
    Philips Research - Eindhoven - The Nederlands

  • regular submissions, see below

Important dates

Submission of full papers
 december 11th
Notification of authors
 january 20th
Final copy of paper
 february 10th
Workshop
 march 25th

Submission
Send a pdf file to  Florence Maraninchi.  For any other format, please contact us in advance.
The submission should not exceed 15 pages in the ENTCS format.


Chair and Organizing Committee

Florence Maraninchi, VERIMAG/INPGrenoble, France
Marc Pouzet, LRI, Paris-sud, France


Programme committee
  • Florence Maraninchi (co-chair) --- VERIMAG/INPG, Grenoble, France
  • Marc Pouzet (co-chair) --- LRI/Paris Sud, France
  • Alessandro Pinto --- UC Berkeley, USA
  • Luca Carloni --- Columbia Univ., NYC, USA
  • Stephen A. Edwards  --- Columbia Univ., NYC, USA
  • Gordon J. Pace --- University of Malta, Msida, Malta
  • Jean-Pierre Talpin --- IRISA, Rennes, France
  • Joaquin Aguado  --- University of Bamberg, Germany
  • Michael Mendler --- University of Bamberg, Germany
  • Klaus Schneider --- University of Kaiserslautern, Germany
  • Daniel Weil --- ATHYS  / Dassault Systèmes, France


Programme

  Session 1:   09:00    until 10:30
  chair : Marc Pouzet

          9:00 : Welcome
                 Florence Maraninchi (VERIMAG / Institut National Polytechnique de Grenoble)
                 and Marc Pouzet (LRI / University of Paris)

          9:15 : Invited talk
                 Use and challenges of synchronous languages for high performance embedded
                 streaming applications.
                 [abstract]
                 Marc Duranton, Principal Scientist
                 Embedded Systems Architectures on Silicon (ESAS)
                 Philips Research - Eindhoven - The Nederlands

  Break 10:30 - 11:00

  Session 2: 11:00 - 12:30
  chair : Florence Maraninchi

          11:00 : An Esterel Virtual Machine for Embedded Systems
                  Becky Plummer, Mukul Kha janchi, Stephen A. Edwards
                  Department of Computer Science, Columbia University, NY, USA


          11:45 : Compiling Esterel for Distributed Execution
                  Li Hsien Yoong, Partha Roop, Zoran Salcic
                  Department of Electrical and Computer Engineering
                  University of Auckland,  New Zealand

  Lunch 12:30 - 14:00

  Session 3: 14:00 - 15:30
  chair : Marc Pouzet

          14:00 : Towards Static Analysis of SIGNAL Programs using Interval Techniques
                  Abdoulaye Gamatie, Thierry Gautier, Paul Le Guernic
                  INRIA, France

          14:45 : Modeling multi-clocked data-flow program using the Generic Modeling Environment
                  Christian Brunette, Jean-Pierre Talpin, Loic Besnard ,Thierry Gautier
                  INRIA, France



  Break 15:30 - 16:00

  Session 4: 16:00  until  18:00
  chair : Florence Maraninchi

          16:00 : Recognition and evaluation of Jevon's language by composing 2-state automata
                  Paul Amblard
                  TIMA, University of Grenoble, France

          16:45 : Special session on education.
                  Reinhard von Hanxleden : Teaching Synchronous Languages at Kiel University                  
                  Marc Pouzet : Foundations of Synchronous Languages
Abstract of the invited talk:

Consumer electronics devices, such as digital TV sets, DVD recorders, mobile phones, and other portable devices are not only real-time devices, but they also rely on heavy computations of streams of data. The increase in performance requirements for stream-oriented processing creates a major gap between the current programmable processors and the actual requirements of applications. To bridge this gap, it is necessary to use parallel architectures consisting of multiple, programmable compute blocks, specifically designed for efficient processing of data streams.


Programming those highly parallel streaming architectures poses also major challenges, both in term of correctness and in terms of performance:difficulty of specifying the non-functional requirements (like latency, processing rate,…), problems in achieving an efficient use of resources (performance- and power-wise),difficulty of managing different forms of parallelism, difficulty and cost of debugging.

Managing the ever-increasing complexity of embedded systems is certainly one of the most important challenges beside power consumption. Complexity will make systems unreliable and unpredictable. We already reach the limits of validation by simulation and worst-case design is no more affordable. Guided by the principles of predictability and compositionality, we will increasingly need to design reliable systems from uncertain components, use higher abstraction level specification, formal methods that allow “correct by construction” designs.


Synchronous languages have proven their efficiency to solve similar issues for real-time critical systems, so it is time now to see if they can also be applied with the same advantages for streaming applications. Several challenges have to be solved:

  • How to describe in the synchronous formalism the specifications of the streaming applications, and the notion of “physical” time and latency,

  • The application domain naturally maps in a hierarchy of “clocks” that are not always a simple sampling of a “master clock”, hence the ideas around multi-synchronous models,

  • Due to physical constraints, the system has some variations in the instant when events really happen, leading to the idea of system that is Locally Asynchronous, but could be considered as Globally Synchronous (LAGS).

  • The implementation will heavily rely on highly parallel hardware, so an efficient mapping of the synchronous model onto parallel programmable systems is also essential.


This talk will present those challenges, and the related potential directions for solving them with synchronous languages, and should trigger discussions during this SLAP’06 workshop.




Affiliation:

Dr. Marc Duranton

Principal Scientist

Embedded Systems Architectures on Silicon (ESAS)

Philips Research - Room 3.33

High Tech Campus 31 - 5656 AE Eindhoven

The Netherlands


Biography:

Dr. Marc Duranton is a principal scientist in the Embedded Systems Architectures on Silicon Group of Philips Research. He has two MSc degrees in electrical engineering, and computer science from Ecole Nationale Supérieure d'Electronique et de Radioélectricité de Grenoble, and Ecole Nationale Supérieure d'Informatique et de Mathématiques Appliquées de Grenoble, respectively, and a PhD (1995) from Institut National Polytechnique de Grenoble, all in France. He worked within Philips Semiconductors in California on several video coprocessors for the TriMedia and Nexperia platforms and is currently working on the next generation compute engine for Philips platform. His research interests include parallel and high performance architectures for video and image processing, system modeling and validation, software optimization, compiler technology, synchronous languages and. He has published several articles and book chapters, and more than 20 patents. He has supervised 4 PhD students and more than 10 MSc students, and has given courses in several engineering schools in France.
Last modification : february 10th, 2006                                                                                                                                 SLAP'2006 web contact