ANR Arpege HELP 2009-2012

Intranet (members only)

Florence Maraninchi — 2010-01-28T08:04:12Z

Related Projects

Florence Maraninchi — 2010-01-21T21:03:17Z

ANR ARESA and ARESA2: part of these projects is devoted to the global (and formal) modeling of energy consumption in sensor networks. In ARESA2, this topic is related to the security aspects. Minalogic openTLM 2006-2010: open tools for the transaction-level modeling of systems-on-a-chip. ANR FoToVP 2006-2009: one of the topics is the extraction of formal models from engineering languages (like SystemC); another topic is the use of analytical models (e.g., the real-time calculus) for (...) - Documents

The proposal

Florence Maraninchi — 2010-01-21T20:57:49Z

State of the Art The focus of research on design of large hardware circuits and Systems-on-Chips has shifted from Register-Transfer Level (RTL) to Electronic System Level (ESL). ESL in fact consists of a multiplicity of sublevels, depending more and less on extra-functional features such as approximate timing. The most famous modeling formalism for ESL design is named SystemC (see the official OSCI site). Defining clear levels for component descriptions allow to devise a platform-based (...) - Documents