Persyval-lab exploratory project 2013-2014 - CESyMPA

CESyMPA Workshop, April 2014, Grenoble

Florence Maraninchi — 2014-03-31T15:55:00Z

In the context of the project CESyMPA funded by Persyval-lab, we organize a workshop. The programme is given below. The talks will take place at Verimag, room Turing. For details on how to come, see the lab webpage.
SCHEDULE
Thursday, April 3, 10:00: Jan Reineke (Sarrebrucken)
Title: PRET DRAM controller: bank privatization for predictability and temporal isolation
Thursday, April 3, 14:00: Florian Brandner (ENSTA-Paritech)
Title: Refinement of Worst-Case Execution Time (...)

- Activities

Master thesis topic: implementing Lustre on top of a manycore architecture

Florence Maraninchi — 2014-02-07T16:56:57Z

Hanan Kanso has just started her master thesis work on a topic closely related to CESyMPA: the implementation of the synchronous language Lustre on top of the manycore architecture built by the company Kalray.
Defense: June 23, 2014, 14:30
The main idea of the master thesis is to try and reproduce for the Kalray MPPA the results of the article "Semantics-preserving multitask implementation of synchronous programs", i.e. the guarantee of input/output determinism, as given by a global (...)

- Activities

Overview

Florence Maraninchi — 2013-02-21T17:11:29Z

CESyMPA: Critical Embedded Systems on Multiprocessor Architectures: Towards a Certifiable HW/SW Solution
People involved:
Florence Maraninchi, VERIMAG (Florence.Maraninchi@imag.fr)
Pascal Raymond, VERIMAG (Pascal.Raymond@imag.fr)
Matthieu Moy, VERIMAG (matthieu.Moy@imag.fr)
Claire Maiza, VERIMAG (Claire.Maiza@imag.fr)
Stéphane Mancini, TIMA (stephane.mancini@imag.fr)
Abbas Sheibanyrad, TIMA (abbas.sheibanyrad@imag.fr)
The current hardware architectures are not suitable for (...)

- General Presentation / page_accueil

Proposal

Florence Maraninchi — 2013-02-21T13:15:08Z

The initial definition of the project.

- Documents