sccheck(1)

NAME
sccheck, sccausal - Causal analysis of ESTEREL programs - Version v5_21

SYNOPSIS
sccheck [options] file ... sccausal [options] file ...

DESCRIPTION
sccheck checks whether a program in sc code is constructive, and, if yes, checks that no single signal can be emitted more than once. The sccheck processor does not generate code. It is normally called via the esterel command with the -Icheck option.

sccausal is the full Esterel constructiveness analyzer. It reads a program in sc code, checks it for constructiveness, and, if it is found constructive, produces a sorted circuit code in ssc format. The sccausal processor is normally called via the esterel command with the -causal option.

The sccheck command is equivalent to sccausal -s -single.

Constructiveness analysis is necessary because Esterel programs can have cyclic dependencies, which translate to combinationally cyclic Boolean control circuits. For more information on constructiveness, see the Esterel v5 documentation.

The sccausal algorithm begins with the FSM representing the control of an Esterel program. It breaks all combinational cycles and assigns unknown values to each circuit node and each input corresponding to a broken cycle. It uses the reached state set to perform an incremental TVF (three-valued functions) computation: the reached states are computed at the same time as the TVFs, at each iteration. We begin by computing the TVFs for the network given the initial state, and at each iteration (each pass through the network), we compute the new TVFs given the current state set (using the cofactor operation), and we use these TVFs to compute the next state set. The iteration continues until no new states are found, or until an unstable state is reached. The final FSM, which is functionally equivalent to the original but contains no combinational cycles, is written in ssc code.

Error messages and warnings are written to the standard error stream. Typical use is:

    esterel -Icheck foo.strl

which performs the following call:

    sccheck < foo.strl

or

    sccausal < game1.sc > game.ssc

or equivalently

    sccausal game2.sc -B game

OPTIONS
The following options are common to all Esterel processors.

-version
    Print the version name on the standard error output stream and terminate, ignoring all other arguments.

-info
    Display various information about the current sccausal processor on the standard error output stream and terminate, ignoring all other arguments.

-access
    Print access rights to the processor on the standard error output stream and terminate, ignoring all other arguments.

-stat
    Print statistics on the standard error stream: CPU times required for parsing the input and performing the causal analysis; physical memory requirement for the process. (Not implemented in current version).

-s  Silent mode: perform parsing and causality analysis but do not produce the ssc code.

-v  Verbose mode.

The following option performs the analysis of the static cycles of the sc program.

-cycles
    Performs a topological sort of the oriented graph corresponding to the sc description. If there are non-trivial strongly connected components (SCC) then it prints an error message giving the coordinates of each SCC and the names of signals that close that particular SCC. If the XES call was not canceled by the user, the error is then shown using the XES interface.

The following options control the algorithm for causality analysis.

-cofactor
    Use a priori information about the reachable states to simplify the BDDs using the cofactor BDD operation. The a priori information is derived from both the relations specified in the Esterel program and information internally derived about mutually exclusive register values. (The latter comes from the selectinc wires; see sc6 format description.) The TVFs for the input signals are cofactored with respect to this information, and the TVFs for the remaining nodes in the network are computed in topological order; no further cofactoring is necessary since the cofactor operation is transitive.

-restrict
    Use a priori information about the reachable states to simplify the BDDs using the BDD restrict operation. Note that since the restrict operation is not transitive, it must be applied to each node after the TVF is computed.

-no_inc
    This options computes the TVFs first and then the reachable state space. It iteratively computes the TVFs (three-valued functions) for each node in the network in topological order, and substitutes the appropriate functions for the cut-cycle inputs. The iteration is repeated until no TVFs change. The set of unstable states is then computed as the set of states in which some node has an undefined value. The circuit is then momentarily assumed constructive, a combinationally-acyclic version is created from the TVFs, and the reachable state set for this FSM is computed. The circuit is declared to be constructive if no unstable state is reached during the reachable state computation.

-inc
    Use the reached state set to perform an incremental TVF computation: the reached states are computed at the same time as the TVFs, at each iteration. We begin by computing the TVFs for the network given the initial state, and at each iteration (each pass through the network), we compute the new TVFs given the current state set (using the cofactor operation), and we use these TVFs to compute the next state set. The iteration continues until no new states are found, or until an unstable state is reached. This is the default option.

-sift
    Use sifting to dynamically reorder the BDD variables when performing BDD operations. Can save a lot of memory, but uses more time.

The following options control the optimization of the data structure that produces the ssc code.

-o1 After causality analysis is complete, optimize the BDDs for the FSM by applying sifting (changing the BDD variable ordering) and simplification (cofactoring with respect to the reachable states). Note that the simplification will have no effect if the -inc option is used.

-o2 After causality analysis is complete, optimize the structure of the resulting FSM (which is represented by BDDs) by removing redundant latches.

The following command is used for verification of single signals

-single
    Checks that for any reached state no single signal is emitted twice (default for sccheck).

The following option is used for testing the sccausal program.

-tvf
    Forces TVF computation and causality analysis even for acyclic circuits. Used for regression testing.

The following options allows to generate BLIF (Berkeley Logic Interchange Format) versions of the processed file:

-cyclic_blif
    If the circuit is cyclic, generates the BLIF version before performing causal analysis. If a basename was specified using the -B option, then the name of this blif file will be cyclic_basename.ssc.blif, cyclic.blif otherwise.

-blif
    If the circuit is causal, generates the acyclic BLIF version after the causal analysis. If a basename was specified using the -B option, then the name of this blif file will be basename.blif, sccausal.blif otherwise.

The following option avoids interfacing with XES simulator:

-no_xes
    By default, when an error is detected, XES simulator is called to graphically display the error. This option avoid the call to XES.

The following option verifies the sc file without ssc code generation:

-check
    Performs causality analysis. If the circuit is causal, checks that for any reached state no single signal is emitted twice. Does not generate the ssc code.

Optimization
Constructiveness analysis can be expensive. The -inc option is usually the best for memory-intensive analysis, because the TVFs are computed only for the reachable states of the system. However, in the case where an intermediate reached state set has a large BDD, it may not be efficient. In addition, this option may require more time as each network-TVF computation is interleaved with a cofactor operation with respect to the reached-state set. In general, for memory-intensive programs, -inc performs better than -restrict, which performs better than -cofactor. The option -sift can be useful in all cases to reduce memory consumption. For CPU-intensive programs, -cofactor performs better than restrict (they are nearly identical operations, but restrict must be applied to every node). The -inc option is more difficult to predict. It requires an application of cofactor at each iteration and hence may take longer; at the same time it uses (possibly) smaller BDDs which may be faster and compensate for the extra cost at each iteration.

BUGS
The current version is under test, and as such, may exhibit anomalies.

DIAGNOSTICS
If the input circuit is non-constructive, a counter-example input sequence is printed and the xes simulator is called to display the error graphically.

SEE ALSO
Esterel documentation. The paper "Constructive Analysis of Cyclic Circuits" by T. Shiple, G. Berry, and H. Touati.

esterel(1), lcsc(1), scssc(1)

IDENTIFICATION
Ecole des Mines de Paris (CMA) and INRIA Sophia-Antipolis.

Written by Tom Shiple & Horia Toma & Amar Bouali.

Based on the TiGeR BDD and FSM library, property of Digital Equipment Corp. and distributed by the XORIX company.