@comment{{This file has been generated by bib2bib 1.98}}
@comment{{Command line: /usr/bin/bib2bib matthieu_moy.bib -c year=2013 -ob 2013.bib}}
@online{libtlmpwt-software,
author = {Claude Helmstetter and Matthieu Moy},
title = {{LIBTLMPWT}: Model Power-Consumption and Temperature in SystemC/TLM},
howpublished = {Published as Free Software (GPL License)},
year = 2013,
url = {http://www-verimag.imag.fr/~moy/?LIBTLMPWT-Model-Power-Consumption}
}
@inproceedings{moy:hal-00761047,
hal_id = {hal-00761047},
url = {http://hal.archives-ouvertes.fr/hal-00761047},
title = {{Parallel Programming with SystemC for Loosely Timed Models: A Non-Intrusive Approach}},
author = {Moy, Matthieu},
abstract = {{The SystemC/TLM technologies are widely accepted in the industry for fast system-level simulation. An important limitation of SystemC regarding performance is that the reference implementation is sequential, and the official semantics makes parallel executions difficult. As the number of cores in computers increase quickly, the ability to take advantage of the host parallelism during a simulation is becoming a major concern. Most existing work on parallelization of SystemC targets cycle-accurate simulation, and would be inefficient on loosely timed systems since they cannot run in parallel processes that do not execute simultaneously. We propose an approach that explicitly targets loosely timed systems, and offers the user a set of primitives to express tasks with duration, as opposed to the notion of time in SystemC which allows only instantaneous computations and time elapses without computation. Our tool exploits this notion of duration to run the simulation in parallel. It runs on top of any (unmodified) SystemC implementation, which lets legacy SystemC code continue running as-it-is. This allows the user to focus on the performance-critical parts of the program that need to be parallelized.}},
keywords = {SystemC; TLM; parallelism; multi-core; loosely-timed},
language = {Anglais},
affiliation = {VERIMAG - VERIMAG - IMAG},
booktitle = {{The Design, Automation, and Test in Europe (DATE)}},
address = {Grenoble, France},
audience = {internationale },
year = {2013},
month = mar,
pdf = {http://www-verimag.imag.fr/~moy/IMG/pdf/sc-during.pdf},
note = {16.4\% accepted as long-paper, Rank A+ GDR SoC-SiP}
}
@inproceedings{bmm-date-13,
title = {System-Level Modeling of Energy in {TLM} for Early Validation of Power and Thermal Management},
author = {Bouhadiba, Tayeb and Moy, Matthieu and Maraninchi, Florence},
booktitle = {Design Automation and Test Europe (DATE)},
address = {Grenoble, France},
month = mar,
team = {SYNC},
url = {http://hal.archives-ouvertes.fr/hal-00807048},
pdf = {http://www-verimag.imag.fr/~moy/publications/granu-date2013.pdf},
year = {2013},
note = {16.4\% accepted as long-paper, Rank A+ GDR SoC-SiP}
}
@inproceedings{helmstetter:hal-00807046,
title = {{Fast and Accurate TLM Simulations using Temporal Decoupling for FIFO-based Communications}},
author = {Helmstetter, Claude and Cornet, J\'er\^ome and Galil\'ee, Bruno and Moy, Matthieu and VIVET, Pascal},
booktitle = {{Design, Automation and Test in Europe (DATE)}},
address = {Grenoble, France},
month = {Mar},
pages = {1185},
url = {http://hal.archives-ouvertes.fr/hal-00807046},
team = {SYNC},
year = {2013},
hal_id = {hal-00807046},
language = {Anglais},
affiliation = {Laboratoire d'Electronique et des Technologies de l'Information - LETI , STMicroelectronics (Grenoble) - ST-GRENOBLE , VERIMAG - IMAG},
audience = {internationale},
pdf = {http://hal.archives-ouvertes.fr/hal-00807046/PDF/TDpaper.pdf},
abstract = {{Untimed models of large embedded systems, generally written using SystemC/TLM, allow the software team to start simulations before the RTL description is available, and then provide a golden reference model to the verification team. For those two purposes, only a correct functional behavior is required, but users are asking more and more for timing estimations early in the design flow. Because companies cannot afford to maintain two simulators for the same chip, only local modifications of the untimed model are considered. A known approach is to add timing annotations into the code and to reduce the number of costly context switches using temporal decoupling, meaning that a process can go ahead of the simulation time before synchronizing again. Our current goal is to apply temporal decoupling to the TLM platform of a many-core SoC dedicated to high performance computing. Part of this SoC communicates using classic memory-mapped buses, but it can be extended with hardware accelerators communicating using FIFOs. Whereas temporal decoupling for memory-based transactions has been widely studied, FIFO-based communications raise issues that have not been addressed before. In this paper, we provide an efficient solution to combine temporal decoupling and FIFO-based communications.}},
note = {acceptance rate: 302/829 = 36.4\% all categories, Rank A+ GDR SoC-SiP}
}
@inproceedings{bouhadiba:hal-00807354,
hal_id = {hal-00807354},
url = {http://hal.archives-ouvertes.fr/hal-00807354},
title = {{Co-Simulation of Functional SystemC TLM Models with Power/Thermal Solvers}},
author = {Bouhadiba, Tayeb and Moy, Matthieu and Maraninchi, Florence and Cornet, J{\'e}r{\^o}me and Maillet-Contoz, Laurent and Materic, Ilija},
abstract = {{Modern systems-on-chips need sophisticated power-management policies to control their power consumption and temperature. These power-management policies are usually implemented partly in software, with hardware support. They need to be validated early, hence power and temperature-aware simulation techniques at the system-level need to be developed. Existing approaches for system-level power and thermal analysis usually either completely abstract the functionality (allowing only simple scenarios to be simulated), or run the functional simulation independently from the non-functional one. The approach presented in this paper allows a coupled simulation of a SystemC/TLM model, possibly including the actual embedded software, with a power and temperature solver such as ATMI or the commercial tool ACEplorer. Power and temperature analysis is done based on the stimuli sent by the SystemC/TLM platform, which in turn can take decisions based on the non-functional simulation.}},
language = {Anglais},
affiliation = {VERIMAG - IMAG , STMicroelectronics (Grenoble), Docea Power},
booktitle = {{Virtual Prototyping of Parallel and Embedded Systems (VIPES)}},
address = {Boston, US},
audience = {internationale },
year = {2013},
month = may,
pdf = {http://hal.archives-ouvertes.fr/hal-00807354/PDF/vipes2013.pdf}
}
This file was generated by bibtex2html 1.98.