List publication All in one, By year.
| [1] |
Florence Maraninchi, Matthieu Moy, Jérôme Cornet, Laurent
Maillet-Contoz, Claude Helmstetter, and Claus Traulsen.
SystemC/TLM Semantics for Heterogeneous System-on-Chip
Validation.
In IEEE, editor, 2008 Joint IEEE-NEWCAS and TAISA
Conference 2008 Joint IEEE-NEWCAS and TAISA Conference,
Montréal Canada, June 2008.
B.6.3, D.2.4, D.3.1, F.4.3, F.3.1, B.8.1.
[ bib |
http ]
SystemC has become a de facto standard for the system-level description of systems-on-a-chip. SystemC/TLM is a library dedicated to transaction level modeling. It allows to define a virtual prototype of a hardware platform, on which the embedded software can be tested. Applying formal validation techniques to SystemC descriptions of SoCs requires that the semantics of the language be formalized. The model of time and concurrency underlying the SystemC definition is intermediate between pure synchrony and pure asynchrony. We list the available solutions for the semantics of SystemC/TLM, and explain how to connect SystemC to existing formal validation tools. Keywords: SystemC; TLM; lustre; spin; promela; semantics; model-checking; verification; model; SoC; System-on-a-Chip |
This file was generated by bibtex2html 1.98.