Workshop on Formal Verification of Analog Circuits

(A satelite event of ETAPS 2005)

April 9th, 2005, Edinburgh, UK

Program (tentative)

08:30-09:00 Registration

09:00-09:30 Introductory remarks: Analog Verification: yet another Buzzword?
O. Maler (Verimag)

09:30-10:30 Invited talk: Challenges in Analog Design: Room for Formal Methods?
Prof. Erich Barke, University of Hannover

10:30-11:00 Break

11:00-11:45 Time Constrained Verification of Analog Circuits using Model-Checking Algorithms
D. Grabowski, D. Platte, L. Hedrich, and E. Barke.

11:45-12:30 Formal Verification of the Quasi-Static Behavior of Mixed-Signal Circuits by Property Checking
M. Freibothe

12:30-14:00 Lunch

14:00-14:45 The Case for Analog Circuit Verification
C. Myers, R. Harrison, D. Walter, N. Seegmiller, and S Little.

14:45-15:30 Analysing the Robustness of Surfing Circuits
S. Yang and M. Greenstreet

15:30-16:00 Break

16:00-16:45Time Domain Verification of Oscillator Circuit Properties
G. Frehse, B. Krogh, O. Maler, and R. Rutenbar

16:45-17:30 Informal discussions