What's been keeping me busy?

Dec 2007 - May 2011 (expected)

Ph.D candidate in Computer Science at the Doctoral School of Computer Science, Applied and Pure Mathematics of Grenoble, France. My advisors are Florence Maraninchi and Matthieu Moy.

May 2008 - May 2011 (expected)

R&D engineer at STMicroelectronics at Grenoble, France.

My thesis in 100 words

Consumer electronic devices are made of hardware (the physical part) and software. In the past, the hardware part had to be fabricated first (e.g. prototype boards), then used for developing the software. Transaction-level modeling (TLM) is an attempt to avoid waiting for the hardware to physically exist before starting the development of software.

TLM models are abstractions of pieces of hardware. These models can be assembled together, but then several questions arise: if two models are independently "faithful" (w.r.t. the real hardware they represent), is the assembly still "faithful"? This is one of the questions I am investigating.

Student monitoring

Portability with respect to execution model in system-on-chip simulation

Rafael Velasquez, short research internship (french TER). 2 Feb - 25 Jun 2010. Subject in French.

Modeling time in system-on-chip simulators

Mohamed El Aissaoui, short research internship (french TER). 1 Feb - 1 Jun 2010. Subject in French.

Design of an experimental simulator for systems-on-chip (full text in English)

Nabila Abdessaied, master's thesis. 5 Jan - 4 Jul 2009. Slides in French. Subject in French.

Selected works

Formal and executable contracts for transaction-level modeling in SystemC (full version)

Bouhadiba, T., Maraninchi, F. and Funchal, G. Verimag, 2009. Technical Report in English.

How to make correct transaction-level models

Funchal, G. Archi'2009 Spring School. Pleumeur-Bodou, 2009. Poster in English.

Components and abstraction levels for system-on-chip

Funchal, G. Synchron'2008 International Workshop. Aussois, 2008. Slides in English.

Components and abstraction levels for system-on-chip

Funchal, G. EMSoC'2008 Workshop. Villard de Lans, 2008. Slides in English.

Composants multi-niveaux d'abstraction pour les systèmes-sur-puce

Funchal, G. EJCP'2008 Summer School. Rennes, 2008. Slides in French.

Comparison of embedded system models: from signals to transactions

Funchal, G. Master's thesis, 2007. Full text in English or slides in French.

Teaching

Sep 2009 - Jan 2010

Project, Transaction-level Modeling of System-on-chip (12h)
ENSIMAG, Grenoble Institute of Technology, France.

Oct 2009 - Nov 2009

Tutorial, Topics of Object Oriented Programming with Java (15h)
Master on Computer Science, Joseph Fourier University, France.

Sep 2008 - Nov 2008

Tutorial, Introduction to Unix (10h30)
ENSIMAG, Grenoble Institute of Technology, France.

May 2008

Project, Introduction to C (11h)
ENSIMAG, Grenoble Institute of Technology, France.

Jan 2008

Project, Computer Architecture, Separate Data/Control path (12h)
ENSIMAG, Grenoble Institute of Technology, France.

Experience

May 2008 - May 2011 (expected)

R&D Engineer at STMicroelectronics at Grenoble, France.

Nov 2007 - April 2008 (6 months)

Research engineer at Joseph Fourier University at Grenoble, France.

Oct 2006 - Jun 2007 (9 months)

Research internship at the VERIMAG Research Lab at Gières, France, during which I worked on the comparison of models of embedded systems.

Feb 2006 - Aug 2006 (7 months)

Engineering internship at STMicroelectronics at Grenoble, France, during which I integrated state-of-the art technology to the SystemC TLM model of the STn8815 Nomadik Multimedia Processor. This system-on-chip is integrated in smartphones like the Nokia N96.

Nov 2003 - Aug 2005 (1 year 10 months)

Working as an undergraduate assistant engineer of the Microelectronics group at the Embedded Systems Lab of the Federal University of Rio Grande do Sul at Porto Alegre, Brazil, I took part of the Brazil-IP project by integrating SystemC RTL IP cores, by writing glue SystemC models and by developing a C/Linux application for testing.

Education

Dec 2007 - May 2011 (expected)

Ph.D, Computer Science at the Doctoral School of Computer Science, Applied and Pure Mathematics of Grenoble, France.

Oct 2006 - Jul 2007

M.Sc, Computer Science at Joseph Fourier University, France. With honors.

Aug 2005 - Jul 2007

M.Eng, Telecommunications at Grenoble Institute of Technology, France. With honors.

Feb 2003 - Aug 2005

B.Eng, Computer Engineering at Federal University of Rio Grande do Sul, Brazil.