Oct 302013

A collaboration with STMicroelectronics
In the context of the OpenES European CATRENE project.

Keywords: transaction-level modeling, systems-on-a-chip, component-based design and modeling, performance properties of hardware/software systems

Short Description: In the framework of a recently started European CATRENE project, the synchrone group at VERIMAG is looking for candidates for a 3-year Phd scholarship starting October 2013. The candidate will work in cooperation with STMicrolectronics and the other academic and industrial partners of the project (including TU Eindhoven, Synopsys NL, …).

The Synchrone group at VERIMAG has been working in close cooperation with STMicroelectronics since 2002 (already 4 co-supervized PhD students graduated). The general topic of the collaboration is transaction-level modeling for systems-on-a-chip, considering functional, timing and energy consumption properties. The language SystemC is the standard of the domain, and the transaction-level modeling principles (TLM) are now normalized. See related publications.

In the context of the project, we propose the following topic: high-level hierarchical component-based models for functional and non-functional (timing, energy) properties of systems-on-a-chip. High-level meaning higher than SystemC/TLM here. We will keep in mind that the models have to be interoperable with existing SystemC/TLM components, and that the models should be executable. The candidate will benefit from the availability of realistic case-studies provided by the industrial partners; he/she will also start from a well developed set of tools and approaches.

The PhD has been defended on May 10, 2017.

  • Pr Laurence Pierre, Univ Grenoble Alpes, president
  • Pr Franco Fummi, University of Verona, reviewer
  • Pr Erika Abraham, University Aachen, reviewer
  • Dr Kim Grüttner, OFFIS, Germany
  • Dr Laurent Maillet-Contoz, STMicroelectronics, France
  • Pr Florence Maraninchi, Univ Grenoble Alpes/Grenoble INP, supervisor

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