Topics: The work on systems-on-a-chip is conducted in collaboration with STMicrolectronics, Grenoble. The Register Transfer Level (RTL) used to be the entry point of the design flow of hardware systems, including systems-on-a-chip (SoCs). However, the simulation environments for such models do not scale up well. Developing and debugging embedded software for these low level models before getting the physical chip from the factory is no longer possible at a reasonable cost. New abstraction levels, such as the Transaction-Level Modeling, have emerged during the last decade. The TLM approach uses a component-based approach, in which hardware blocks are modules communicating with so-called transactions. The TLM models are used for early development of the embedded software, because the high level of abstraction allows a fast simulation. This new abstraction level requires that SoCs be described in some non-deterministic asynchronous way, with new synchronization mechanisms, quite different from the implicit synchronization of synchronous circuit descriptions. SystemC is a C++ library used for the description of SoCs at different levels of abstraction, from cycle accurate to purely functional models. It comes with a simulation environment, and has become a standard. SystemC offers a set of primitives for the description of parallel activities representing the physical parallelism of the hardware blocks. The TLM level of abstraction can be described with SystemC. Recent work at Verimag/Synchrone focused on the modeling of time and energy consumption at high levels of abstraction, typically TLM. We now work on general high-level models for heterogeneous embedded systems, which can be simulated very early in the design cycle. The idea is to specify the components by very abstract non-deterministic contract-like specifications, so that their composition can be executed very early, before all the details of their implementation is known.