Jun 302013
Students and Collaborations:


Smart cities currently rely on the deployment of dedicated IoT infrastructures, each from a given stakeholder, and mostly for monitoring applications. We investigate a solution to transform these vertical organizations into horizontal ones, to allow several stakeholders to share the infrastructure, for both monitoring and control applications. Our proposal uses state- based models inherited from typical embedded systems models, to represent sensors, actuators and portions of space like streets, crossings, etc. These models are automatically translated into REST resources to provide a standard interface for monitoring and control purposes. We also propose a distributed infrastructure able to execute applications with various timing requirements and conflicting needs. We illustrate these ideas with a proof of concept implementation, a programming model and guidelines for application programmers.


Control-oriented Models for a shared IoT Infrastructure in Smart Cities

Mar 012013
Students, Projects, Collaborations:
  • Hanan Kanso (Master 2014)
  • Amaury Graillat (Master 2015)
  • Moustapha Lo (PhD 2015-2018), Nicolas Valot (Airbus Helicopters), CIFRE PhD
  • Pascal Raymond, Matthieu Moy (Verimag), Amaury Graillat (CIFRE PhD, Kalray)
  • Projects: CESyMPA, CAPACITES


The current hardware architectures are not suitable for critical embedded systems, because they are designed for average performance, offering transparent mechanisms at several levels (from the pre-fetching mechanisms in memory controllers to the routing algorithms in networks on a chip, including the very principle of a cache, load balancing techniques, etc.). All these mechanisms are a major obstacle to predictability and determinism, as required by certification authorities. The question of how to design an embedded system for the critical domains, using modern hardware architectures, therefore raises a huge interest, both in companies, and in academia. There is no satisfactory solution yet.

In the context of the project CESyMPA (Persyval-Lab, 2013-2014), we advocate that these topics deserve a new and fresh look, “forgetting” about the constraints of existing components or software solutions. In this project, we aim at exploring ways to implement critical systems as software running on multiprocessor architectures, in such a way that the complete solution be simple and provably deterministic, therefore acceptable by certification authorities. We would like to come up with a clear idea of what could be an ideal hardware architecture and design flow for “predictable-by-construction” critical embedded systems. Even if it is not feasible for a number of reasons, ranging from hardware fabrication problems to economic viability, this is scientifically worth trying because it would give an estimation of the distance between such an ideal solution and what exists now, and help identifying the tricky problems with the current hardware.

In the context of the project CAPACITES, and the CIFRE PhDs of Moustapha Lo and Amaury Graillat, we study the use of the  Kalray MPPA manycore processor for critical real-time applications.

Sep 302004



Current work:

In the context of the OpenES project, we designed a very general and high-level notion of a component for hardware/software systems, for which functional  properties can be specified in a contract-like formalism. Contrary to a lot of component models at this level of abstraction, our framework is executable. A non-deterministic component can be “executed” if, given inputs, we are able to generate random outputs such that the non-deterministic contract that links inputs and outputs is satisfied. This method relies on constraint solvers. We defined a formalism and execution engine compatible with existing SystemC/TLM components.

We are now starting to work on the idea of a “quality of use” contract for a HW/SW component. In the execution of a system made of several components (some of them given in full details, some of them described by their contracts only), we will define warnings, able to  identify situations in which, for instance,  a piece of software makes a non-optimal use of a HW component (e.g., if it offers a DMA-like memory transfer, but the SW does not use it).

Previous work:

The work on components is inspired by the various notions of components we’ve worked with in the following domains:

  • Embedded control, especially with synchronous languages; case-studies in SCADE (the commercial programming environment based on Lustre); previous work on contracts for reactive systems (see Lionel Morel, PhD 2001-2005).
  • Transaction-Level Modeling (TLM) of systems-on-a-chip
  • Virtual Prototyping of various embedded and communicating systems (e.g., sensor networks)

Main Publications:

Sep 302002

Current ProjectsOpenES

Students involved: Yuliia Romenska

Previous projects and students (2002-):  HELP, OpenTLM, G. Funchal, J. Cornet, C. Helmstetter,  M. Moy

Topics: The work on systems-on-a-chip is conducted in collaboration with STMicrolectronics, Grenoble.  The Register Transfer Level (RTL) used to be the entry point of the design flow of hardware systems, including systems-on-a-chip (SoCs). However, the simulation environments for such models do not scale up well. Developing and debugging embedded software for these low level models before getting the physical chip from the factory is no longer possible at a reasonable cost. New abstraction levels, such as the Transaction-Level Modeling, have emerged during the last decade. The TLM approach uses a component-based approach, in which hardware blocks are modules communicating with so-called transactions. The TLM models are used for early development of the embedded software, because the high level of abstraction allows a fast simulation. This new abstraction level requires that SoCs be described in some non-deterministic asynchronous way, with new synchronization mechanisms, quite different from the implicit synchronization of synchronous circuit descriptions. SystemC is a C++ library used for the description of SoCs at different levels of abstraction, from cycle accurate to purely functional models. It comes with a simulation environment, and has become a standard. SystemC offers a set of primitives for the description of parallel activities representing the physical parallelism of the hardware blocks. The TLM level of abstraction can be described with SystemC. Recent work at Verimag/Synchrone focused on the modeling of time and energy consumption at high levels of abstraction, typically TLM. We now work on general high-level models for heterogeneous embedded systems, which can be simulated very early in the design cycle. The idea is to specify the components by very abstract non-deterministic contract-like specifications, so that their composition can be executed very early, before all the details of their implementation is known.