Vincent Morice, PhD 2018-2021

 PhD Students, Research  Comments Off on Vincent Morice, PhD 2018-2021
Jan 112019
 

CIFRE with STMicroelectronics

A collaboration with J. Cornet and L. Maillet-Contoz

Adding Diagnostic Features to Digital Twins for Systems-on-a-Chip

The “main feature” of a transaction-level (TL) model is to simulate accurately the execution of an embedded software on a given hardware. Nowadays, this feature is complemented by “diagnosis” features. For instance, if the embedded software programs invalid values or values that would cause an invalid usage of a given hardware block, an error message is reported.

We foresee the need to extend the scope of these diagnosis to other areas such as: performance, low-power, safety. The general idea is that a TL model can be used to report about improper or sub-optimal usages of the hardware, based on the intention of the SoC architect. For instance, a TL model could report that a given software is doing a memory transfer “manually” instead of actually delegating the task to a low-power DMA and putting the CPU in sleep mode. More generally, it would be interesting to quantify to which extent the software achieves the best possible usage of the given hardware for a given criteria (energy efficiency, feature coverage, etc.).

Sep 302015
 

  • Antoine Dechambre, Master II, 2017 (with Pascal Raymond)
  • Amaury Graillat, Master II R, 2014-2015  (with Matthieu Moy)
  • Hanan Kanso, Master II R, 2013-2014 (with Matthieu Moy)
  • Abdelhaq Beladjine, master II R 2009-2010
  • Sofiane Kara Mostefa, master II R 2009-2010
  • Laurie Lugrin, Master II R, 2008-2009 (with Laurent Mounier)
  • Nicolas Berthier, Master II R, 2007-2008 (with Christophe Rippert)
  • Quentin Meunier, Master II R, 2006-2007 (with Karine Altisen)
  • Giovanni Funchal, Master IIR, 2006-2007 (with Matthieu Moy)
  • Tayeb Sofiane Bouhadiba, Master IIR, 2005-2006
  • Muhammad Muzammil Shahbaz, Master IIR, 2004-2005 (with Matthieu Moy)
  • David Stauch, Master IIR 2003-2004 (with Karine Altisen)
  • Jacques Ndjeng Ndjeng, DEA 2002-2003
  • Aurélie Clodic , DEA 2001-2002
  • Lionel Morel, DEA 2000-2001
  • Fabien Gaucher, DEA 1999-2000
  • Yann Rémond, DEA 1997-1998
  • Traian Popovici, Master Diploma, Rumania, 1995-1996
  • Muriel Vachon, DEA 1990-1991
Oct 302013
 

A collaboration with STMicroelectronics
In the context of the OpenES European CATRENE project (Open ESL Technologies for Next Generation Embedded Systems).

Keywords: transaction-level modeling, systems-on-a-chip, component-based design and modeling, performance properties of hardware/software systems

See online: https://tel.archives-ouvertes.fr/tel-01681425

Summary:

The work presented in this thesis deals with modeling, specification and testing of models of Systems-on-a-Chip (SoCs) at the transaction abstraction level and higher. SoCs are heterogeneous: they comprise both hardware components and processors to execute embedded software, which closely interacts with hardware. SystemC-based Transaction Level Modeling (TLM) has been very successful in providing high-level executable component-based models for SoCs, also called virtual prototypes (VPs). These models can be used early in the design flow for the development of the software and the validation of the actual hardware. For SystemC/TLMvirtual prototypes, Assertion-Based Verification (ABV) allows property checking early in the design cycle,helping to find bugs early in the model and to save time and effort that are needed for their fixing. TL model scan be over-constrained, which means that they do not represent all the behaviors of the hardware, and thus,do not allow detection of some malfunctions of the prototype. Our contributions consist of two orthogonal and complementary parts: On the one hand, we identify sources of over-constraints in TL models appearing due to the order of interactions between components, and propose a notion of loose-ordering which allows to remove these over-constraints. On the other hand, we propose a generalized stubbing mechanism which allows the very early simulation with SystemC/TLM virtual prototypes.We propose a set of patterns to capture loose-ordering properties, and define a direct translation of these patterns into SystemC monitors. Our generalized stubbing mechanism enables the early simulation with SystemC/TLM virtual prototypes, in which some components are not entirely determined on the values of the exchanged data, the order of the interactions and/or the timing. Those components have very abstract specifications only, in the form of constraints between inputs and outputs. We show that essential synchronization problems between components can be captured using our simulation with stubs. The mechanism is generic;we focus only on key concepts, principles and rules which make the stubbing mechanism implementable and applicable for real, industrial case studies. Any specification language satisfying our requirements (e.g., loose-orderings) can be used to specify the components, i.e., it can be plugged in the stubbing framework. We provide a proof of concept to demonstrate the interest of using the simulation with stubs for very early detection and localization of synchronization bugs of the design.

The PhD has been defended on May 10, 2017.
Committee:

  • Pr Laurence Pierre, Univ Grenoble Alpes, president
  • Pr Franco Fummi, University of Verona, reviewer
  • Pr Erika Abraham, University Aachen, reviewer
  • Dr Kim Grüttner, OFFIS, Germany
  • Dr Laurent Maillet-Contoz, STMicroelectronics, France
  • Pr Florence Maraninchi, Univ Grenoble Alpes/Grenoble INP, supervisor
Oct 152013
 

A collaboration with Orange Labs.

Title Shared self-configuring models and software infrastructures for Smart City monitoring and control.

  • Co-supervized by Didier Donsez, LIG
  • In collaboration with Gilles Privat, Orange Labs.

See online https://tel.archives-ouvertes.fr/tel-01689910

Summary

Nowadays cities face several challenges and are concerned by ecological, energetic, economical, and demographical aspects. Smart cities, equipped with sensors, actuators, and digital infrastructures, are meant to tackle these issues.Current smart cities are operated by several actors without sharing sensor data or accesses to the actuators. This is a vertical organization, in which each actor deploys its own sensors and actuators, and manages its own digital infrastructure. Each actor may be interested in a different aspect of city management, for instance traffic management, air control, etc. The current trend is a transition towards a more horizontal organization, based on an open and shared mediation platform. In such a platform, sensor data and accesses to actuators can be shared among several actors. The costs related to nfrastructure deployment and management are therefore reduced for each individual actor. This PhD is a contribution to this volution towards horizontal organizations, with open and shared platforms. We propose: (1) an abstraction layer for the ontrol and supervision of the city; (2) a concurrency management mechanism; (3) a coordination mechanism that helps haring actuators; (4) a proof-of-concept implementation of these contributions. The abstraction layer we propose helps users control and supervise a city. It is based upon formal models inspired by the ones used in the programming of reactive systems. They represent the physical elements present in each smart city, with genericity principles. In order to ease application development, the interface of those models is made uniform. Since applications, especially control ones, may ave real-time constraints, we also list the constraints this poses on distributed infrastructures. As soon as actuators are shared, conflicts may occur between users. Our proposals include a concurrency management mechanism, based on eservation principles. We also provide a coordination mechanism for the users to be able to perform several actions in an tomic way.All these principles have been implemented as a proof of concept. We review several use cases, to demonstrate he potential benefits of our proposals.

The PhD has been defended on June 6, 2017.
Committee:

  • Robert de Simone, INRIA, reviewer
  • Thierry Monteil, Assistant Professor, HDR, INSA Toulouse, Reviewer
  • Michael Mrissa, Professor, University of Pau
  • Didier Donsez, Professor, Univ. Grenoble-Alpes, supervisor
  • Florence Maraninchi, Professor, Univ. Grenoble-Alpes, co-supervisor
  • Gilles Privat, Orange Labs
Apr 302013