Sep 302015
 

  • Amaury Graillat, Master II R, 2014-2015  (with Matthieu Moy)
  • Hanan Kanso, Master II R, 2013-2014 (with Matthieu Moy)
  • Abdelhaq Beladjine, master II R 2009-2010
  • Sofiane Kara Mostefa, master II R 2009-2010
  • Laurie Lugrin, Master II R, 2008-2009 (with Laurent Mounier)
  • Nicolas Berthier, Master II R, 2007-2008 (with Christophe Rippert)
  • Quentin Meunier, Master II R, 2006-2007 (with Karine Altisen)
  • Giovanni Funchal, Master IIR, 2006-2007 (with Matthieu Moy)
  • Tayeb Sofiane Bouhadiba, Master IIR, 2005-2006
  • Muhammad Muzammil Shahbaz, Master IIR, 2004-2005 (with Matthieu Moy)
  • David Stauch, Master IIR 2003-2004 (with Karine Altisen)
  • Jacques Ndjeng Ndjeng, DEA 2002-2003
  • Aurélie Clodic , DEA 2001-2002
  • Lionel Morel, DEA 2000-2001
  • Fabien Gaucher, DEA 1999-2000
  • Yann Rémond, DEA 1997-1998
  • Traian Popovici, Master Diploma, Rumania, 1995-1996
  • Muriel Vachon, DEA 1990-1991
Oct 302013
 

A collaboration with STMicroelectronics
In the context of the OpenES European CATRENE project.

Keywords: transaction-level modeling, systems-on-a-chip, component-based design and modeling, performance properties of hardware/software systems

Short Description: In the framework of a recently started European CATRENE project, the synchrone group at VERIMAG is looking for candidates for a 3-year Phd scholarship starting October 2013. The candidate will work in cooperation with STMicrolectronics and the other academic and industrial partners of the project (including TU Eindhoven, Synopsys NL, …).

The Synchrone group at VERIMAG has been working in close cooperation with STMicroelectronics since 2002 (already 4 co-supervized PhD students graduated). The general topic of the collaboration is transaction-level modeling for systems-on-a-chip, considering functional, timing and energy consumption properties. The language SystemC is the standard of the domain, and the transaction-level modeling principles (TLM) are now normalized. See related publications.

In the context of the project, we propose the following topic: high-level hierarchical component-based models for functional and non-functional (timing, energy) properties of systems-on-a-chip. High-level meaning higher than SystemC/TLM here. We will keep in mind that the models have to be interoperable with existing SystemC/TLM components, and that the models should be executable. The candidate will benefit from the availability of realistic case-studies provided by the industrial partners; he/she will also start from a well developed set of tools and approaches.

 

Oct 152013
 

A collaboration with Orange Labs.

Title Shared self-configuring models and software infrastructures for Smart City monitoring and control.

  • Co-supervized by Didier Donsez, LIG
  • In collaboration with Gilles Privat, Orange Labs.

Summary

Most city-scale ICT applications rely on their own vertically integrated and dedicated infrastructure, foregoing the benefits that could result from sharing sensors, networks, software enablers and, crucially, consolidated data and information originating from these. The objective of this research project is to evolve a shared horizontalized software infrastructure for cities, providing proxies of physical entities to different smart city applications. These proxies have to capture and consolidate the real-time state of these entities for applications to monitor and control them. They also have to rely on a hierarchy of models that, together, are generic enough to be automatically matched to the corresponding entities through an iterative self-configuration process.

 

Apr 302013