Sep 302015
 

  • Antoine Dechambre, Master II, 2017 (with Pascal Raymond)
  • Amaury Graillat, Master II R, 2014-2015  (with Matthieu Moy)
  • Hanan Kanso, Master II R, 2013-2014 (with Matthieu Moy)
  • Abdelhaq Beladjine, master II R 2009-2010
  • Sofiane Kara Mostefa, master II R 2009-2010
  • Laurie Lugrin, Master II R, 2008-2009 (with Laurent Mounier)
  • Nicolas Berthier, Master II R, 2007-2008 (with Christophe Rippert)
  • Quentin Meunier, Master II R, 2006-2007 (with Karine Altisen)
  • Giovanni Funchal, Master IIR, 2006-2007 (with Matthieu Moy)
  • Tayeb Sofiane Bouhadiba, Master IIR, 2005-2006
  • Muhammad Muzammil Shahbaz, Master IIR, 2004-2005 (with Matthieu Moy)
  • David Stauch, Master IIR 2003-2004 (with Karine Altisen)
  • Jacques Ndjeng Ndjeng, DEA 2002-2003
  • Aurélie Clodic , DEA 2001-2002
  • Lionel Morel, DEA 2000-2001
  • Fabien Gaucher, DEA 1999-2000
  • Yann Rémond, DEA 1997-1998
  • Traian Popovici, Master Diploma, Rumania, 1995-1996
  • Muriel Vachon, DEA 1990-1991
Jul 012015
 

A collaboration with Airbus Helicopters.

Title Critical Real-Time Embedded Systems on Manycore Architectures

  • Co-supervized by Pascal Raymond
  • In collaboration with Nicolas Valot, Airbus Helicopters.

PhD defended on Feb. 22, 2019.
Committee:

  • Emmanuel Grolleau, ISAE – ENSMA, reviewer
  • Claire Pagetti, ONERA, reviewer
  • Giuseppe Lipari, University of Lille, examinator
  • Florence Maraninchi, Grenoble INP, supervisor
  • Pascal Raymond,  CNRS, co-supervisor
  • Nicolas Valot, Airbus Helicopters
Oct 302013
 

A collaboration with STMicroelectronics
In the context of the OpenES European CATRENE project (Open ESL Technologies for Next Generation Embedded Systems).

Keywords: transaction-level modeling, systems-on-a-chip, component-based design and modeling, performance properties of hardware/software systems

See online: https://tel.archives-ouvertes.fr/tel-01681425

Summary:

The work presented in this thesis deals with modeling, specification and testing of models of Systems-on-a-Chip (SoCs) at the transaction abstraction level and higher. SoCs are heterogeneous: they comprise both hardware components and processors to execute embedded software, which closely interacts with hardware. SystemC-based Transaction Level Modeling (TLM) has been very successful in providing high-level executable component-based models for SoCs, also called virtual prototypes (VPs). These models can be used early in the design flow for the development of the software and the validation of the actual hardware. For SystemC/TLMvirtual prototypes, Assertion-Based Verification (ABV) allows property checking early in the design cycle,helping to find bugs early in the model and to save time and effort that are needed for their fixing. TL model scan be over-constrained, which means that they do not represent all the behaviors of the hardware, and thus,do not allow detection of some malfunctions of the prototype. Our contributions consist of two orthogonal and complementary parts: On the one hand, we identify sources of over-constraints in TL models appearing due to the order of interactions between components, and propose a notion of loose-ordering which allows to remove these over-constraints. On the other hand, we propose a generalized stubbing mechanism which allows the very early simulation with SystemC/TLM virtual prototypes.We propose a set of patterns to capture loose-ordering properties, and define a direct translation of these patterns into SystemC monitors. Our generalized stubbing mechanism enables the early simulation with SystemC/TLM virtual prototypes, in which some components are not entirely determined on the values of the exchanged data, the order of the interactions and/or the timing. Those components have very abstract specifications only, in the form of constraints between inputs and outputs. We show that essential synchronization problems between components can be captured using our simulation with stubs. The mechanism is generic;we focus only on key concepts, principles and rules which make the stubbing mechanism implementable and applicable for real, industrial case studies. Any specification language satisfying our requirements (e.g., loose-orderings) can be used to specify the components, i.e., it can be plugged in the stubbing framework. We provide a proof of concept to demonstrate the interest of using the simulation with stubs for very early detection and localization of synchronization bugs of the design.

The PhD has been defended on May 10, 2017.
Committee:

  • Pr Laurence Pierre, Univ Grenoble Alpes, president
  • Pr Franco Fummi, University of Verona, reviewer
  • Pr Erika Abraham, University Aachen, reviewer
  • Dr Kim Grüttner, OFFIS, Germany
  • Dr Laurent Maillet-Contoz, STMicroelectronics, France
  • Pr Florence Maraninchi, Univ Grenoble Alpes/Grenoble INP, supervisor
Oct 152013
 

A collaboration with Orange Labs.

Title Shared self-configuring models and software infrastructures for Smart City monitoring and control.

  • Co-supervized by Didier Donsez, LIG
  • In collaboration with Gilles Privat, Orange Labs.

See online https://tel.archives-ouvertes.fr/tel-01689910

Summary

Nowadays cities face several challenges and are concerned by ecological, energetic, economical, and demographical aspects. Smart cities, equipped with sensors, actuators, and digital infrastructures, are meant to tackle these issues.Current smart cities are operated by several actors without sharing sensor data or accesses to the actuators. This is a vertical organization, in which each actor deploys its own sensors and actuators, and manages its own digital infrastructure. Each actor may be interested in a different aspect of city management, for instance traffic management, air control, etc. The current trend is a transition towards a more horizontal organization, based on an open and shared mediation platform. In such a platform, sensor data and accesses to actuators can be shared among several actors. The costs related to nfrastructure deployment and management are therefore reduced for each individual actor. This PhD is a contribution to this volution towards horizontal organizations, with open and shared platforms. We propose: (1) an abstraction layer for the ontrol and supervision of the city; (2) a concurrency management mechanism; (3) a coordination mechanism that helps haring actuators; (4) a proof-of-concept implementation of these contributions. The abstraction layer we propose helps users control and supervise a city. It is based upon formal models inspired by the ones used in the programming of reactive systems. They represent the physical elements present in each smart city, with genericity principles. In order to ease application development, the interface of those models is made uniform. Since applications, especially control ones, may ave real-time constraints, we also list the constraints this poses on distributed infrastructures. As soon as actuators are shared, conflicts may occur between users. Our proposals include a concurrency management mechanism, based on eservation principles. We also provide a coordination mechanism for the users to be able to perform several actions in an tomic way.All these principles have been implemented as a proof of concept. We review several use cases, to demonstrate he potential benefits of our proposals.

The PhD has been defended on June 6, 2017.
Committee:

  • Robert de Simone, INRIA, reviewer
  • Thierry Monteil, Assistant Professor, HDR, INSA Toulouse, Reviewer
  • Michael Mrissa, Professor, University of Pau
  • Didier Donsez, Professor, Univ. Grenoble-Alpes, supervisor
  • Florence Maraninchi, Professor, Univ. Grenoble-Alpes, co-supervisor
  • Gilles Privat, Orange Labs
Jun 302013
 
Students and Collaborations:

Topic:

Smart cities currently rely on the deployment of dedicated IoT infrastructures, each from a given stakeholder, and mostly for monitoring applications. We investigate a solution to transform these vertical organizations into horizontal ones, to allow several stakeholders to share the infrastructure, for both monitoring and control applications. Our proposal uses state- based models inherited from typical embedded systems models, to represent sensors, actuators and portions of space like streets, crossings, etc. These models are automatically translated into REST resources to provide a standard interface for monitoring and control purposes. We also propose a distributed infrastructure able to execute applications with various timing requirements and conflicting needs. We illustrate these ideas with a proof of concept implementation, a programming model and guidelines for application programmers.

Publications:

Control-oriented Models for a shared IoT Infrastructure in Smart Cities

Apr 302013
 

Mar 012013
 
Students, Projects, Collaborations:
  • Hanan Kanso (Master 2014)
  • Amaury Graillat (Master 2015)
  • Moustapha Lo (PhD 2015-2018), Nicolas Valot (Airbus Helicopters), CIFRE PhD
  • Pascal Raymond, Matthieu Moy (Verimag), Amaury Graillat (CIFRE PhD, Kalray)
  • Projects: CESyMPA, CAPACITES

Topic:

The current hardware architectures are not suitable for critical embedded systems, because they are designed for average performance, offering transparent mechanisms at several levels (from the pre-fetching mechanisms in memory controllers to the routing algorithms in networks on a chip, including the very principle of a cache, load balancing techniques, etc.). All these mechanisms are a major obstacle to predictability and determinism, as required by certification authorities. The question of how to design an embedded system for the critical domains, using modern hardware architectures, therefore raises a huge interest, both in companies, and in academia. There is no satisfactory solution yet.

In the context of the project CESyMPA (Persyval-Lab, 2013-2014), we advocate that these topics deserve a new and fresh look, “forgetting” about the constraints of existing components or software solutions. In this project, we aim at exploring ways to implement critical systems as software running on multiprocessor architectures, in such a way that the complete solution be simple and provably deterministic, therefore acceptable by certification authorities. We would like to come up with a clear idea of what could be an ideal hardware architecture and design flow for “predictable-by-construction” critical embedded systems. Even if it is not feasible for a number of reasons, ranging from hardware fabrication problems to economic viability, this is scientifically worth trying because it would give an estimation of the distance between such an ideal solution and what exists now, and help identifying the tricky problems with the current hardware.

In the context of the project CAPACITES, and the CIFRE PhDs of Moustapha Lo and Amaury Graillat, we study the use of the  Kalray MPPA manycore processor for critical real-time applications.

Sep 302012
 

  CESyMPA — Persyval Lab, 2013-2014

Critical Embedded Systems on Multiprocessor Architectures:
Towards a Certifiable HW/SW Solution

The current hardware architectures are not suitable for critical embedded systems, because they are designed for average performance, offering transparent mechanisms at several levels (from the pre-fetching mechanisms in memory controllers to the routing algorithms in networks on a chip, including the very principle of a cache, load balancing techniques, etc.). All these mechanisms are a major obstacle to predictability and determinism, as required by certification authorities. The question of how to design an embedded system for the critical domains, using modern hardware architectures, therefore raises a huge interest, both in companies, and in academia. There is no satisfactory solution yet.

We think that these topics deserve a new and fresh look, “forgetting” about the constraints of existing components or software solutions. In this project, we aim at exploring ways to implement critical systems as software running on multiprocessor architectures, in such a way that the complete solution be simple and provably deterministic, therefore acceptable by certification authorities. We would like to come up with a clear idea of what could be an ideal hardware architecture and design flow for “predictable-by-construction” critical embedded systems. Even if it is not feasible for a number of reasons, ranging from hardware fabrication problems to economic viability, this is scientifically worth trying because it would give an estimation of the distance between such an ideal solution and what exists now, and help identifying the tricky problems with the current hardware.

ARESA2 — ANR 2009-2013

To connect to the IP world dynamic wireless sensor networks in a secure and energy efficient way.

HELP — ANR 2009-2013 (leader)

The HELP project focuses on functional and non-functional high-level models for the design of low-power embedded systems. The need for low-power systems is now well admitted, in the domain of embedded systems in general. This is particularly true for sensor networks or consumer electronics (mobile phones and all kinds of portable devices), because of lifetime constraints. But this is also true for other (non autonomous) embedded systems, in a world concerned with sustainable development.

openTLM — Minalogic 2006-2010

Tools for the virtual prototyping of systems-on-a-chip
openTLM is devoted to open tools for the virtual prototyping of systems-on-a-chip based on Transaction-Level-Modeling (TLM)

FoToVP — ANR 2006-2010 (leader)

Formal Tools for the Virtual Prototyping of Embedded Systems
In the context of past or current projects involving industrial partners from various application domains, the participants of FoToVP have observed several approaches for the design of complex and/or critical embedded systems, based on the notion of virtual prototyping. This allowed us to identify clearly where there is a need for formal tools. We started studying the benefits of formal methods and tools in the other projects, with the constraints of particular application domains, and with practical objectives in mind. Some recurring problems appeared, that need to be investigated further, independently of these application domains, and with less constraining short-term practical objectives. In this project called FoToVP, standing for “Formal Tools for Virtual Prototyping of Embedded Systems’’, we would like to study these recurring problems, in order to develop more fundamental and generic results. The motivations are clearly related to industrial applications, and the applicability of the project results will be evaluated with respect to these industrial practises and applications.

ARESA — ANR (RNRT) 2006-2009

Sensor networks have been researched and deployed for decades already; their wireless extension, however, has witnessed a tremendous upsurge in recent years. This is mainly attributed to the unprecedented operating conditions of wireless sensor networks (WSNs), i.e. (i) a potentially enormous amount of sensor nodes; (ii) reliably operating under stringent energy constraints.
WSNs allow for an untethered sensing of the environment. It is anticipated that within a few years, sensors will be deployed in a variety of scenarios, ranging from environmental monitoring to health care, from the public to the private sector, etc. They will be battery-driven and deployed in great numbers in an ad-hoc fashion, requiring communication protocols and embedded system components to run in an utmost energy efficient manner.
Prior to large-scale deployment, however, a gamut of problems has to be solved which relates to various issues, such as the extraction of application scenarios, design of suitable software and hardware architectures, development of communication and organization protocols, validation and first steps of prototyping, etc.

ALIDECS / ACI “Sécurité & Informatique” French Programme, 2004-2007

Languages and Tool-Chain for the Development of Safe Embedded Components.
This project addresses large size critical embedded systems, for which reuse is becoming crucial. The objective is to study an integrated development environment for the construction and use of safe embedded components. The use of an appropriate programming language being one of the key points contributing to safety in computer systems, we will favour a “language” approach for all aspects.

RISE / IST-2001-38117

CTRL-a ARC INRIA 2003-2004

Indo-French Collaboration 2000-2002 IFCPAR project nr. 2202-1, in cooperation with TIFR, Bombay

SYRF Esprit “Long Term Research” Project 22703 1996-1999