Jun 302013
 
Students and Collaborations:

Topic:

Smart cities currently rely on the deployment of dedicated IoT infrastructures, each from a given stakeholder, and mostly for monitoring applications. We investigate a solution to transform these vertical organizations into horizontal ones, to allow several stakeholders to share the infrastructure, for both monitoring and control applications. Our proposal uses state- based models inherited from typical embedded systems models, to represent sensors, actuators and portions of space like streets, crossings, etc. These models are automatically translated into REST resources to provide a standard interface for monitoring and control purposes. We also propose a distributed infrastructure able to execute applications with various timing requirements and conflicting needs. We illustrate these ideas with a proof of concept implementation, a programming model and guidelines for application programmers.

Publications:

Control-oriented Models for a shared IoT Infrastructure in Smart Cities

Apr 302013
 

Mar 012013
 
Students, Projects, Collaborations:
  • Hanan Kanso (Master 2014)
  • Amaury Graillat (Master 2015)
  • Moustapha Lo (PhD 2015-2018), Nicolas Valot (Airbus Helicopters), CIFRE PhD
  • Pascal Raymond, Matthieu Moy (Verimag), Amaury Graillat (CIFRE PhD, Kalray)
  • Projects: CESyMPA, CAPACITES

Topic:

The current hardware architectures are not suitable for critical embedded systems, because they are designed for average performance, offering transparent mechanisms at several levels (from the pre-fetching mechanisms in memory controllers to the routing algorithms in networks on a chip, including the very principle of a cache, load balancing techniques, etc.). All these mechanisms are a major obstacle to predictability and determinism, as required by certification authorities. The question of how to design an embedded system for the critical domains, using modern hardware architectures, therefore raises a huge interest, both in companies, and in academia. There is no satisfactory solution yet.

In the context of the project CESyMPA (Persyval-Lab, 2013-2014), we advocate that these topics deserve a new and fresh look, “forgetting” about the constraints of existing components or software solutions. In this project, we aim at exploring ways to implement critical systems as software running on multiprocessor architectures, in such a way that the complete solution be simple and provably deterministic, therefore acceptable by certification authorities. We would like to come up with a clear idea of what could be an ideal hardware architecture and design flow for “predictable-by-construction” critical embedded systems. Even if it is not feasible for a number of reasons, ranging from hardware fabrication problems to economic viability, this is scientifically worth trying because it would give an estimation of the distance between such an ideal solution and what exists now, and help identifying the tricky problems with the current hardware.

In the context of the project CAPACITES, and the CIFRE PhDs of Moustapha Lo and Amaury Graillat, we study the use of the  Kalray MPPA manycore processor for critical real-time applications.

Sep 302012
 

  CESyMPA — Persyval Lab, 2013-2014

Critical Embedded Systems on Multiprocessor Architectures:
Towards a Certifiable HW/SW Solution

The current hardware architectures are not suitable for critical embedded systems, because they are designed for average performance, offering transparent mechanisms at several levels (from the pre-fetching mechanisms in memory controllers to the routing algorithms in networks on a chip, including the very principle of a cache, load balancing techniques, etc.). All these mechanisms are a major obstacle to predictability and determinism, as required by certification authorities. The question of how to design an embedded system for the critical domains, using modern hardware architectures, therefore raises a huge interest, both in companies, and in academia. There is no satisfactory solution yet.

We think that these topics deserve a new and fresh look, “forgetting” about the constraints of existing components or software solutions. In this project, we aim at exploring ways to implement critical systems as software running on multiprocessor architectures, in such a way that the complete solution be simple and provably deterministic, therefore acceptable by certification authorities. We would like to come up with a clear idea of what could be an ideal hardware architecture and design flow for “predictable-by-construction” critical embedded systems. Even if it is not feasible for a number of reasons, ranging from hardware fabrication problems to economic viability, this is scientifically worth trying because it would give an estimation of the distance between such an ideal solution and what exists now, and help identifying the tricky problems with the current hardware.

ARESA2 — ANR 2009-2013

To connect to the IP world dynamic wireless sensor networks in a secure and energy efficient way.

HELP — ANR 2009-2013 (leader)

The HELP project focuses on functional and non-functional high-level models for the design of low-power embedded systems. The need for low-power systems is now well admitted, in the domain of embedded systems in general. This is particularly true for sensor networks or consumer electronics (mobile phones and all kinds of portable devices), because of lifetime constraints. But this is also true for other (non autonomous) embedded systems, in a world concerned with sustainable development.

openTLM — Minalogic 2006-2010

Tools for the virtual prototyping of systems-on-a-chip
openTLM is devoted to open tools for the virtual prototyping of systems-on-a-chip based on Transaction-Level-Modeling (TLM)

FoToVP — ANR 2006-2010 (leader)

Formal Tools for the Virtual Prototyping of Embedded Systems
In the context of past or current projects involving industrial partners from various application domains, the participants of FoToVP have observed several approaches for the design of complex and/or critical embedded systems, based on the notion of virtual prototyping. This allowed us to identify clearly where there is a need for formal tools. We started studying the benefits of formal methods and tools in the other projects, with the constraints of particular application domains, and with practical objectives in mind. Some recurring problems appeared, that need to be investigated further, independently of these application domains, and with less constraining short-term practical objectives. In this project called FoToVP, standing for “Formal Tools for Virtual Prototyping of Embedded Systems’’, we would like to study these recurring problems, in order to develop more fundamental and generic results. The motivations are clearly related to industrial applications, and the applicability of the project results will be evaluated with respect to these industrial practises and applications.

ARESA — ANR (RNRT) 2006-2009

Sensor networks have been researched and deployed for decades already; their wireless extension, however, has witnessed a tremendous upsurge in recent years. This is mainly attributed to the unprecedented operating conditions of wireless sensor networks (WSNs), i.e. (i) a potentially enormous amount of sensor nodes; (ii) reliably operating under stringent energy constraints.
WSNs allow for an untethered sensing of the environment. It is anticipated that within a few years, sensors will be deployed in a variety of scenarios, ranging from environmental monitoring to health care, from the public to the private sector, etc. They will be battery-driven and deployed in great numbers in an ad-hoc fashion, requiring communication protocols and embedded system components to run in an utmost energy efficient manner.
Prior to large-scale deployment, however, a gamut of problems has to be solved which relates to various issues, such as the extraction of application scenarios, design of suitable software and hardware architectures, development of communication and organization protocols, validation and first steps of prototyping, etc.

ALIDECS / ACI “Sécurité & Informatique” French Programme, 2004-2007

Languages and Tool-Chain for the Development of Safe Embedded Components.
This project addresses large size critical embedded systems, for which reuse is becoming crucial. The objective is to study an integrated development environment for the construction and use of safe embedded components. The use of an appropriate programming language being one of the key points contributing to safety in computer systems, we will favour a “language” approach for all aspects.

RISE / IST-2001-38117

CTRL-a ARC INRIA 2003-2004

Indo-French Collaboration 2000-2002 IFCPAR project nr. 2202-1, in cooperation with TIFR, Bombay

SYRF Esprit “Long Term Research” Project 22703 1996-1999

Oct 022006
 

Students and collaborations:

  • David Stauch (PhD 2006)
  • Karine Altisen

Main Publications:

Sep 302004
 

Projects:

Students:

  • Tayeb Bouhadiba, PhD 2006-2010
  • Giovanni Funchal, PhD 2007-2011
  • Yuliia Romenska

Current work:

In the context of the OpenES project, we design a very general and high-level notion of a component for hardware/software systems, for which functional and extra-functional properties can be specified in a contract-like formalism. Contrary to a lot of component models at this level of abstraction, our framework is executable. A non-deterministic component can be “executed” if, given inputs, we are able to generate random outputs such that the non-deterministic contract that links inputs and outputs is satisfied. This method relies on constraint solvers. We aim at defining a formalism and execution engine compatible with existing SystemC/TLM components.

Previous work:

The work on components is inspired by the various notions of components we’ve worked with in the following domains:

  • Embedded control, especially with synchronous languages; case-studies in SCADE (the commercial programming environment based on Lustre); previous work on contracts for reactive systems (see Lionel Morel, PhD 2001-2005).
  • Transaction-Level Modeling (TLM) of systems-on-a-chip
  • Virtual Prototyping of various embedded and communicating systems (e.g., sensor networks)

Main Publications:

 

Sep 302002
 

Current ProjectsOpenES

Students involved: Yuliia Romenska

Previous projects and students (2002-):  HELP, OpenTLM, G. Funchal, J. Cornet, C. Helmstetter,  M. Moy

Topics: The work on systems-on-a-chip is conducted in collaboration with STMicrolectronics, Grenoble.  The Register Transfer Level (RTL) used to be the entry point of the design flow of hardware systems, including systems-on-a-chip (SoCs). However, the simulation environments for such models do not scale up well. Developing and debugging embedded software for these low level models before getting the physical chip from the factory is no longer possible at a reasonable cost. New abstraction levels, such as the Transaction-Level Modeling, have emerged during the last decade. The TLM approach uses a component-based approach, in which hardware blocks are modules communicating with so-called transactions. The TLM models are used for early development of the embedded software, because the high level of abstraction allows a fast simulation. This new abstraction level requires that SoCs be described in some non-deterministic asynchronous way, with new synchronization mechanisms, quite different from the implicit synchronization of synchronous circuit descriptions. SystemC is a C++ library used for the description of SoCs at different levels of abstraction, from cycle accurate to purely functional models. It comes with a simulation environment, and has become a standard. SystemC offers a set of primitives for the description of parallel activities representing the physical parallelism of the hardware blocks. The TLM level of abstraction can be described with SystemC. Recent work at Verimag/Synchrone focused on the modeling of time and energy consumption at high levels of abstraction, typically TLM. We now work on general high-level models for heterogeneous embedded systems, which can be simulated very early in the design cycle. The idea is to specify the components by very abstract non-deterministic contract-like specifications, so that their composition can be executed very early, before all the details of their implementation is known.

 Publications:

Sep 302000
 

Projects, Students and Main Collaborations:

  • Projects: ARESA, ARESA2
  • PhD Students: Ludovic Samper, Nicolas Berthier
  • Collaborations: Orange Labs
  • Other Verimag people involved: Laurent Mounier, Karine Altisen, Stéphane Devismes, Pascal Lafourcade

Main Publications: