sc-during is a library that can be used on top of SystemC to write efficient parallel simulators.
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New publications
- Recent Publications
- Klaus Havelund, Doron Peled, Dogan Ulus: First order temporal logic monitoring with BDDs
- Ezio Bartocci, Jyotirmoy V. Deshmukh, Alexandre Donzé, Georgios E. Fainekos, Oded Maler, Dejan Nickovic, Sriram Sankaranarayanan: Specification-Based Monitoring of Cyber-Physical Systems: A Survey on Theory, Tools and Applications
- Stéphane Devismes, David Ilcinkas, Colette Johnen: Self-Stabilizing Disconnected Components Detection and Rooted Shortest-Path Tree Maintenance in Polynomial Steps
- Benjamin Farinier, Sebastien Bardin, Richard Bonichon, Marie-Laure Potet: Model Generation for Quantified Formulas: A Taint-Based Approach
- Jannik Dreier, Maxime Puys, Marie-Laure Potet, Pascal Lafourcade, Jean-Louis Roch: Formally Verifying Flow Properties in Industrial Systems
- Karine Altisen, Pierre Corbineau: Composition certifié d'algorithmes autostabilisants silencieux
Jobs and internships
- Jobs and internships
- Phd Position: Vulnerability search in Industrial Control Systems
- Phd Proposal : Inférence de modèles de faute pour simulation d’attaques sur composants sécurisés
- Phd proposal : Optimisation de l’évaluation et des tests de sécurité des systèmes cyber-physiques par analyse des canaux auxiliaires
- PHD proposal: Data Mining Dynamic Behaviors using Signal Temporal Logic
- Post-Doc and/or Research Engineer positions on Software Security
- [M1 internship] Modeling of Graph Topologies Using Coq
