@incollection{Moy05b,
title = { Chapter 5.9, Formal Verification },
author = {Moy, Matthieu},
year = {2005},
booktitle = {Transaction-Level Modeling with {SystemC}. {TLM} Concepts and Applications for Embedded Systems},
pages = {190--206},
publisher = {Springer},
team = {SYNC},
}
bibtex
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Récentes
- Marius Bozga, Radu Iosif, Joseph Sifakis: Verification of component-based systems with recursive architectures
- David Monniaux, Léo Gourdin, Sylvain Boulmé, Olivier Lebeltel: Testing a Formally Verified Compiler
- Karine Altisen, Alain Cournier, Geoffrey Defalque, Stéphane Devismes: Pour battre à l'unisson, il faut que tous les chemins viennent de Rome
- Karine Altisen, Stéphane Devismes, Anaïs Durand, Colette Johnen, Franck Petit: Self-stabilizing Systems in Spite of High Dynamics
Offres d'emploi et stages
- Offres d'emploi et stages
- [Master] Implementation of critical applications on multi-core : execution mode analysis to reduce interferences
- Bourses PERSYVAL de M2
- Junior professorship chair on verifiable / explainable artificial intelligence
- Poste de professeur des universités (section 27)
- [Funded PhD/PostDoc] Countermeasures to (transient) Side-Channel Attacks in a Formally Verified Compiler
- [Funded PhD] Annotations de sécurité pour compilateur optimisant formellement vérifié
- [Funded PhD] Quantitative analysis of software security against adaptive attacks
- [Master] Analyzing fault parameters triggering timing anomalies
- [Master] Exploration by model-checking of timing anomaly cancellation in a processor
- [Master] Formal Methods for the Verification of Self-Adapting Distributed Systems
- [Master] Modular Analysis for Formal Verification of Integrated Circuits at Transistor Level
- [Master]Leakage in presence of an active and adaptive adversary
- [PostDoc] Implementation of critical applications on multi-core : execution mode analysis to reduce interferences