Verimag

bibtex

@inproceedings{BHJ+11,
    title = {Designing a {CPU} model: from a pseudo-formal document to fast code },
    author = {Blanqui, Fr\'ed\'eric and Helmstetter, Claude and Joloboff, Vania and Monin, Jean-Fran\c{c}ois and Shi, Xiaomu},
    month = {01},
    year = {2011},
    booktitle = {Proceedings of the 3rd Workshop on Rapid Simulation and Performance Evaluation: Methods and Tools},
    address = {Heraklion, Greece},
    note = {Best Paper Award},
    team = {DCS},
    abstract = {For validating low level embedded software, engineers use simulators that take the real binary as input. Like the real hardware, these full-system simulators are organized as a set of components. The main component is the CPU simulator (ISS), because it is the usual bottleneck for the simulation speed, and its development is a long and repetitive task. Previous work showed that an ISS can be generated from an Architecture Description Language (ADL). In the work reported in this paper, we generate a CPU simulator directly from the pseudo-formal descriptions of the reference manual. For each instruction, we extract the information describing its behavior, its binary encoding, and its assembly syntax. Next, after automatically applying many optimizations on the extracted information, we generate a SystemC/TLM ISS. We also generate tests for the decoder and a formal specification in Coq. Experiments show that the generated ISS is as fast and stable as our previous hand-written ISS.},
}

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