Verimag

bibtex

@inproceedings{CMM+12,
    title = { {Co-Simulation of a SystemC TLM Virtual Platform with a Power Simulator at the Architectural Level: Case of a Set-Top Box} },
    author = {Cornet, J\'er\^ome and Maillet-Contoz, Laurent and Materic, Ilija and Kaiser, Sylvian and Boussetta, Hela and Bouhadiba, Tayeb and Moy, Matthieu and Maraninchi, Florence},
    month = {Jun},
    year = {2012},
    booktitle = {{Design Automation Conference}},
    address = {San Francisco, {\'E}tats-Unis},
    pages = {SESSION 10U: USER TRACK},
    team = {SYNC},
    hal_id = {hal-00716051}, keywords = {power estimation; temperature; systemc; transaction-level modeling}, language = {Anglais}, affiliation = {STMicroelectronics (Grenoble) - ST-GRENOBLE , Docea Power , VERIMAG - VERIMAG - IMAG}, audience = {internationale},
    abstract = {{The ability to perform power estimation early in the design flow is becoming more and more critical as power optimization requirements grow. For now, standalone power simulators allow such estimation, based on typical stimuli described in a use-case scenario. We propose a co-simulation of SystemC TLM platforms with a Power model. This way, the Power model benefits from more realistic stimuli. In addition, it is possible to provide real-time information from the Power model back to the SystemC TLM simulation, such as temperature values.}},
}

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