Verimag

bibtex

@phdthesis{Chk10b,
    title = { {Modelling real-time embedded systems using AADL for the automatic generation of applications formally verified} },
    author = {Chkouri, Mohamed Yassin},
    month = {Apr},
    year = {2010},
    type = {Theses},
    school = {{Universit{\'e} Joseph-Fourier - Grenoble I}},
    team = {DCS, RSD},
    keywords = {Embedded Systems ; Real-Time ; Translation ; Formal Verification ; AADL ; BIP ; Syst{\`e}mes Embarqu{\'e}s ; Temps-R{\'e}el ; Transformation ; V{\'e}rification Formelle}, pdf = {https://tel.archives-ouvertes.fr/tel-00516152/file/thA_se_final.pdf},
}

URL

Publication Sections


Contact | Site Map | Site powered by SPIP 3.0.26 + AHUNTSIC [CC License]

info visites 873929