Verimag

bibtex

@inproceedings{MMC+08,
    title = { {S}ystem{C}/{TLM} {S}emantics for {H}eterogeneous {S}ystem-on-{C}hip {V}alidation },
    author = {Maraninchi, Florence and Moy, Matthieu and Cornet, J\'er\^ome and Maillet-Contoz, Laurent and Helmstetter, Claude and Traulsen, Claus},
    month = {June},
    year = {2008},
    booktitle = {2008 {J}oint {IEEE}-{NEWCAS} and {TAISA} {C}onference},
    address = {{M}ontr'eal {C}anada},
    note = {{B}.6.3, {D}.2.4, {D}.3.1, {F}.4.3, {F}.3.1, {B}.8.1},
    pages = {unknown},
    publisher = {IEEE},
    team = {SYNC},
    keywords = {{S}ystem{C}; {TLM}; lustre; spin; promela; semantics; model-checking; verification; model; {S}o{C}; {S}ystem-on-a-{C}hip}, language = {{A}nglais}, affiliation = {{VERIMAG} - {VERIMAG} - {IMAG} - {CNRS} : {UMR}5104 - {U}niversit'e {J}oseph {F}ourier - {G}renoble {I} - {I}nstitut {N}ational {P}olytechnique de {G}renoble - {INPG} - {STM}icroelectronics ({G}renoble) - {ST}-{GRENOBLE} - {STM}icroelectronics - {STM}icroelectronics ({C}rolles) - {ST}-{CROLLES} - {STM}icroelectronics - {L}aboratoire {F}ranco-{C}hinois d'{I}nformatique, d'{A}utomatique et de {M}ath'ematiques {A}ppliqu'ees - {LIAMA} - {I}nstitute of {A}utomation, {C}hinese {A}cademy of {S}ciences - {C}hinese {A}cademy of {S}cience - {INRA} - {INRIA} - {BRGM} - {CIRAD} - {CNRS} - {FORMES} - {LIAMA} - {INRIA} - {T}singhua {U}niversity / {B}eijing - {LIAMA} - {I}nformatic {K}iel {U}niversity - {C}hristian-{A}lbrechts-{U}niversit{"a}t, {K}iel}, audience = {internationale},
    abstract = {{S}ystem{C} has become a de facto standard for the system-level description of systems-on-a-chip. {S}ystem{C}/{TLM} is a library dedicated to transaction level modeling. {I}t allows to define a virtual prototype of a hardware platform, on which the embedded software can be tested. {A}pplying formal validation techniques to {S}ystem{C} descriptions of {S}o{C}s requires that the semantics of the language be formalized. {T}he model of time and concurrency underlying the {S}ystem{C} definition is intermediate between pure synchrony and pure asynchrony. {W}e list the available solutions for the semantics of {S}ystem{C}/{TLM}, and explain how to connect {S}ystem{C} to existing formal validation tools. },
}

URL

Publication Sections


Contact | Site Map | Site created with SPIP 2.1.26 + AHUNTSIC [CC License]

Logged in visitors: 11 ; visits: 432695