Verimag

bibtex

@inproceedings{FM11a,
    title = { {jTLM}: an Experimentation Framework for the Simulation of Transaction-Level Models of Systems-on-Chip },
    author = {Funchal, Giovanni and Moy, Matthieu},
    year = {2011},
    booktitle = {Design, Automation and Test in Europe (DATE)},
    team = {SYNC},
    abstract = {Virtual prototypes are simulators used in the consumer electronics industry. Transaction-level Modeling (TLM) is a widely used technique for designing such virtual prototypes. In particular, they allow for early development of embedded software. The SystemC modeling language is the current industry standard for developing virtual prototypes. Our experience suggests that writing TLM models exclusively in SystemC leads sometimes to confusion between modeling concepts and their implementation, and may be the root of some known bad practices. This paper introduces jTLM, an experimentation framework that allow us to study the extent to which common modeling issues come from a more fundamental constraint of the TLM approach. We focus on a discussion of the two modes of simulation scheduling: cooperative and preemptive. We confront the implications of these two modes on the way of designing TLM models, the software bugs exposed by the simulators and the performance. },
}

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