Verimag

bibtex

@inproceedings{FMM+11,
    title = { Faithfulness Considerations for Virtual Prototyping of Systems-on-Chip },
    author = {Funchal, Giovanni and Moy, Matthieu and Maillet-Contoz, Laurent and Maraninchi, Florence},
    month = {jan},
    year = {2011},
    booktitle = {3rd Workshop on: Rapid Simulation and Performance Evaluation: Methods and Tools (RAPIDO)},
    address = {Heraklion, Crete, Greece},
    team = {SYNC},
    abstract = {Virtual prototypes are simulators used in the consumer electronics industry. They enable the development of embedded software before the real, physical hardware is available, hence providing important gains in speed of development and time-to-market. Transaction-level Modeling (TLM) is a widely used technique for designing such virtual prototypes. Its main insight is that many micro-architectural details (i.e. caches, fifos and pipelines) can be omitted from the model as they should not impact the behavior perceived from a software programmer's point-of-view. In this paper, we shall see that this assumption is not always true, specially for low-level software (e.g. drivers). As a result, there may be bugs in the software which are not observable on a TLM virtual prototype, designed according to the current modeling practices. We call this a "faithfulness" issue. Our experience shows that many engineers are not aware of this issue. Therefore, we provide an in-depth and intuitive explanation of the sort of bugs that may be missed. We claim that, to a certain extent, modified TLM models can be faithful without losing the benefits in terms of time-to-market and ease of modeling. However, further investigation is required to understand how this could be done in a more general framework. },
}

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