SYRF Project

Task 6.2: Mixed Controller/Data-path Design

Abstract of deliverable 6.2.2

We have explored the generation of VHDL-RTL code from Signal source specification. VHDL-RTL is the Register Transfer Level of VHDL, i.e., a low level code in the VHDL design suite. This requires that Signal itself is used to actually specify an architecture at RTL level. This is achieved by using the notion of a Signal process as a direct counterpart of a hardware component. From this RTL architecture specification in Signal, the generation of VHDL-RTL is immediate, by the way of performing a direct mapping from the Signal-RTL architecture down to the VHDL-RTL architecture.

Simulations, verifications, optimizations, and exploration of the design space, are thus performed within the Signal environment itself, before VHDL code is generated. For the previous delivery, we have indicated how  Signal clocks are encoded in a way suitable to VHDL-RTL generation, from which the translation principles follow.

This year, two main routes have been explored, resulting in significant changes in VHDL code generation.

1. Pushing the work of previous year further, we have explored the possibility of using the Signal source specification for deducing the possibility of resource sharing  for the different items constituting the architecture, namely
• variables and registers
• basic blocks
• path segments and busses
and the like, in a uniform way. To this end, we systematically exploit the hierarchical clock-and-dependency structure which the compiler computes as a result from Signal source code analysis. The automatic discovery of mutual exclusion, in a hierarchical way, is the basis for such type of optimisation. The delivery focusses on this part of the work.
 
2. Using the same Signal based architecture description to generate a model, also written in  Signal , for emulating the real-time consumption of the considered hardware architecture. This is a profiling service. This model could then be submitted to the formal timing analysers studied in task 4/5.3.

Achieved Results:

1. A pre-prototype has been developed implementing the automatic detection of resource sharing and resulting rearchitecturing of the considered circuit, see the deliverable.
2. A prototype has been developed for Signal program profiling. This prototype is currently under integration in the framework of the overall Signal/DC+-compiler. This should probably be demonstrated at the review.

1. A. Kountouris, C. Wolinski. Hierarchical Conditional Dependency Graphs for Mutual Exclusiveness Identification. to appear in the proceedings of VLSI'99, Goa, India, Jan. 7-10, 1999. (compressed postscript ~58K)
2. A. Kountouris, C. Wolinski. Combining Speculative Execution and Conditional Resource Sharing to Efficiently Schedule Conditional Behaviors. to appear in the proceedings of ASP-DAC'99, Hong-Kong, Jan. 18-21, 1999. (compressed postscript ~45K)
3. A. Kountouris, C. Wolinski. False Path Analysis based on a Hierarchical Control Representation. IEEE proceedings of ISSS'98, Hsinchu, Taiwan, R.O.C., December 2-4, 1998.
4. A. Kountouris, C. Wolinski. Hierarchical Conditional Dependency Graphs for Conditional Resource Sharing. IEEE proceedings of Euromicro 98, 24th-27th, August 1998, Vasteras, Sweden, IEEE Computer Society Press.
5. A. Kountouris, C. Wolinski. Efficient Mutual Exclusiveness Identification in Hierarchical Conditional Dependency Graphs. IRISA Research Report, under review, to appear.