Simulations, verifications, optimizations, and exploration of the design space, are thus performed within the Signal environment itself, before VHDL code is generated. Signal processes, specified at a functional level, are substituted by their refined Signal models of hardware components, or alternatively by a VHDL-RTL component, imported within Signal as a black-box module equipped with its interface behavioral description. Signal-V4 provides means for describing such interfaces, using clock equations and directed graphs labelled by clocks (the notion of dependency graph labelled by clocks is described in detail in task task 4.1).
As Signal clocks are an abstract notion, of higher level than the corresponding notion of clock in hardware, part of the translation from Signal to VHDL consists in rewriting the Signal specification into Signal itself, but in such a way that all Signal clocks are now represented as boolean signals synchronized to a unique master clock, which is also the fastest one. In other words, every signal x is transformed into a strobed signal <h(x),v(x)> which is synchronous with a signal clk that represents the circuit main clock. In the pair <h(x),v(x)>, h(x) represents the boolean clock of x, it is a boolean signal with clock clk which takes the value true if and only if x is present; then, v(x) is a signal which carries the actual value of x when the latter is present, and otherwise carries a don't care. As optimizations in Signal are based on a clock and dependency calculus, prior to performing optimizations, clocks can be attached, either to signals, or alternatively to hardware components.
Achieved Results:
A pre-prototype of translator implementing this approach has been developed,
which takes Signal.tra intermediate format as an input, and
produces VHDL-RTL as an output. This translator, however, has limitations, as
the following features of Signal are not supported:
Publications: