SYRF Project

Approach:

Data-flow formalisms for synchronous reactive programming, such as Lustre and Signal, essentially compile into definitional equation systems with additional registers. This compilation process amounts to a great extend to a clock resolution calculus. Variables and operators in the equation system may belong to various types.

On the other hand imperative languages like Esterel (but also most graphical formalisms of Statechart influence) produce purely boolean equation systems, with additional boolean variables inserted to drive memory operations on data, these operations being stored in a side action table. This corresponds to a separation between control and data flows.

The work package WP 2 of the project intends to integrate / unify both these points of view. Several routes have been pursued at present to achieve a combination of synchronous formalisms: 

• combination on the source level by extending the data-flow model by ``modes'' of operation,
  
  
• combination on the level of an intermediate code
  (a)  by cross-compiling between different existing intermediate codes, and by then linking on the level of one intermediate code
  (b) compiling into, and linking the same intermediate code on a unified semantical basis.

Achieved Results:

• The concept of a mode as an additional feature for a data flow language has been formalized in [1], and it has been proved that modes are compositional with regard to parallel composition, 
  
  
• The Esterel compiler of INRIA (Sophia Antipolis) has been extended to generate DC-code by realizing a SC to DC translator (SC and DC are common intermediate formats for control based resp. data flow languages) . The translator was tested on the SAAB case study which have been specified both, in an Esterel version, and in a mixed Lustre/Esterel version: the control part of the aircraft has been implemented in Esterel, and the data part in Lustre.
  
  
• An orthogonal integration of all the languages has been described in (3,4), and has been prototypic ally implemented under the name of the Synchronie Workbench (2). By orthogonal integration we understand a combination of synchronous languages which allows freely to call a module of a synchronous language in another languages. Beside compilers and linkers the workbench provides graphical interfaces for Argos in the Statechart tradition, and a uniform simulation environment.

Publications:

1. GMD-EES.
   The Synchronie Workbench
2. L.Holenderski, A.Poigné.
   The Multi-Paradigm Language LEA
   Annex A.2.1a
3. L.Holenderski.
   Translating LEA to Synchronous Components.
   Arbeitspapiere der GMD, Nr. 1090
4. A. Ressouche, R. de Simone
   The SCDC processor, illustrated on a SYRF case study.
   Internal report. Annex A.2.1b
5. F.Maranchini, Y.Rémond
   Mode-Automata: About Modes and States in Reactive Systems.
   Research Report, Verimag. Annex A.2.1c