Workshop on Formal Verification of Analog
Circuits
(A satelite event of ETAPS 2005)
April 9th, 2005, Edinburgh, UK
Organizers: Thao Dang, Bruce Krogh, Oded Maler and Rob Rutenbar
While
formal verification has become part of the design process of
digital circuits, its application to analog and mixed-signal design
is only in its infancy. This is mainly due to the fact that the
mathematical models for such circuits are very different from the
discrete, finite-state transition systems that underly verification
of digital systems. Such models are based on continuous dynamical
systems governed by differential equations and their verification calls
for different techniques, like those developed in the analysis
of hybrid systems. These workshop intends to bring together
practitioners
in circuit design and in EDA tools together with researchers in
verification of discrete and hybrid systems in order to understand the
problems faced by designers of analog circuits and to see what support
can be provided by existing and new verification techniques.
Program committee:
Pierluigi Daglio, STM, Agrate
Thao Dang, Verimag, Grenoble
Avi Efrati, Intel, Haifa
Lars Hedrich, University of Hannover
Bruce Krogh, CMU, Pittsburgh
Oded Maler, Verimag, Grenoble
Ursula Martin, Queen Mary University
Jean-Paul Morin, STM, Crolles
Mark Moulin, IBM, Haifa
Chris Myers, University of Utah
Rob Rutenbar, CMU, Pittsburgh
Submission of abstracts:
Authors are invited to send 8-10 pages abstracts to FAC.Workshop@imag.fr not
later than January 15th.
Notification of acceptance: February 7th
Revised versions of the presentations will be published in the electronic journal ENTCS.
Preliminary program