Verimag

FoToVP

ANR, ARA-SETIN, 2006-2009

Formal Tools for the Virtual Prototyping of Embedded Systems.

Introduction

In the context of past or current projects involving industrial partners from various application domains, the participants of FoToVP have observed several approaches for the design of complex and/or critical embedded systems, based on the notion of virtual prototyping. This allowed us to identify clearly where there is a need for formal tools. We started studying the benefits of formal methods and tools in the other projects, with the constraints of particular application domains, and with practical objectives in mind. Some recurring problems appeared, that need to be investigated further, independently of these application domains, and with less constraining short-term practical objectives. In this project called FoToVP, standing for ``Formal Tools for Virtual Prototyping of Embedded Systems’’, we would like to study these recurring problems, in order to develop more fundamental and generic results. The motivations are clearly related to industrial applications, and the applicability of the project results will be evaluated with respect to these industrial practises and applications.

Keywords:

  • virtual prototyping
  • embedded systems,
  • components,
  • synchronous languages, engineering languages (SystemC, ...)

Partners

Verimag people Involved

  • Florence Maraninchi
  • Matthieu Moy
  • Karine Altisen
  • Yanhong Liu

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