Verimag

Seminar details

Seminar Room 1, ground floor (Building IMAG)
10 October 2017 - 10h30
Learning Mealy Machines with Timers
by Frits Vaandrager from Radboud University, Netherlands



Abstract: (joint work with Bengt Jonsson)

Active automata learning is emerging as a highly effective bug finding technique, with applications in areas such as banking cards, network protocols and legacy software. Timing often plays a crucial role in these applications, but cannot be handled adequately by existing algorithms. Even though there has been significant progress on algorithms for active learning of timed models, these approaches are not yet practical due to limited expressivity and/or high complexity.

In order to address this problem, we introduce a simple model of Mealy machines with timers that is able to model the timing behavior of a large class of practical systems, and present a new and efficient algorithm for active learning of this type of automata.




Contact | Site Map | Site powered by SPIP 3.0.26 + AHUNTSIC [CC License]

info visites 894467