Verimag

Seminar details

CTL
24 October 2012 - 14h00
Optimizing DMA Data Transfers for Embedded Multi-Cores
by Selma Saidi from VERIMAG



Abstract: Multiprocessor system on chip (MPSoC) such as the CELL processor or the more recent Platform2012 are heterogeneous multi-core architectures, with a powerful host processor and a computation fabric, consisting of several smaller cores, whose intended role is to act as a general purpose programmable accelerator. Therefore computation-intensive (and parallelizable) parts of the application initially intended to be executed by the host processor are offloaded to the multi-cores for execution.
These parts of the application are often data intensive, operating on large arrays of data initially stored in a remote off-chip memory whose access time is about 100 times slower than that of the cores local memory. Accessing data in the off-chip memory becomes then a main bottleneck for performance.
A major characteristic of these platforms is a software controlled local memory storage rather than a hidden cache mechanism where data movement in the memory hierarchy, typically performed using a DMA (Direct Memory Access) engine, are explicitly managed by the software.
In this thesis, we attempt to optimize such data transfers in order to reduce/hide the off-chip memory latency.



Jury:

- Mr. Oded Maler
Directeur de Recherche, CNRS, Directeur de thèse

- Mr. Luca Benini
Professeur, Université de bologne, Rapporteur

- Mr. Albert Cohen
Directeur de Recherche, INRIA, Rapporteur

- Mr. Eric Flamand
Directeur de la division AST Computing, STMicroelectronics, Examinateur

- Mr. Ahmed Bouajjani
Professeur, Université Paris Diderot (paris 7), Examinateur

- Mr. Bruno Jego
Equipe Application à AST Computing, STMicroelectronics, Examinateur

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