Verimag

Seminar details

CTL
29 October 2012 - 14h00
On Computer-Aided Design-Space Exploration for Multi-Cores
by Jean-François KEMPF from VERIMAG



Abstract: The growing complexity of embedded systems calls for modeling formalisms that can be simulated and analyzed to explore the space of design alternatives. This thesis describes the development of a modeling formalism and tools for design space exploration at early stages of the development.
On one hand we introduce the formalism of Duration Probabilistic Automata (DPA), that can be viewed as timed automata where the intervals of temporal uncertainty are interpreted probabilistically. We developed a piecewise analytic approach to compute performance measures for such systems and study the synthesis of schedulers which are expected-time optimal.
On the other hand we developed DESPEX (DEsign SPace EXplorer), a tool for performance evaluation of high-level models. Given an application and an architecture description with a specific deployment scheme, the tool provides performance evaluation (latency, power consumption ...) at early design stages in the design flow. We demonstrate the usage of the tool on several case studies.



Jury :
- Mr. Oded Maler, Directeur de Recherche CNRS, Directeur de thèse
- Mr. Marius Bozga, Ingénieur de Rechercheur CNRS, Encadrant
- Pr. Kim G. Larsen, Aalborg University, Rapporteur
- Pr. Bruce Krogh, Carnegie Mellon, Rapporteur
- Pr. Boudewijn R. Haverkort, University of Twente, Examinateur
- Pr. Eugène Asarin, Université Denis Diderot Paris 7, Examinateur
- Mr. Fahim Rahim, ATRENTA, Examinateur

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